SEMICONDUCTOR DEVICES
    2.
    发明申请

    公开(公告)号:US20220416045A1

    公开(公告)日:2022-12-29

    申请号:US17583314

    申请日:2022-01-25

    Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. the first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

    INTEGRATED CIRCUITS FOR CONTROLLING SLEW RATES OF SIGNALS

    公开(公告)号:US20180159517A1

    公开(公告)日:2018-06-07

    申请号:US15405893

    申请日:2017-01-13

    Abstract: An integrated circuit includes a differential signal driver that receives a first signal from a first input terminal, receives a second signal, which is a differential signal of the first signal, from a second input terminal, outputs a first output signal corresponding to the first signal to a first output terminal, and outputs a second output signal corresponding to the second signal to a second output terminal. The integrated circuit further includes a first capacitor unit connected to the first output terminal and controlling a slew rate of the first output signal based on a first capacitance, a second capacitor unit connected to the second output terminal and controlling a slew rate of the second output signal based on a second capacitance, and a phase selection unit that receives the first signal and provides the first signal to the second capacitor unit, and that receives the second signal and provides the second signal to the first capacitor unit, so as to control the slew rates of the first and second output signals.

    METHOD AND APPARATUS FOR DISASTER NOTIFICATION
    6.
    发明申请
    METHOD AND APPARATUS FOR DISASTER NOTIFICATION 有权
    用于灾害通知的方法和装置

    公开(公告)号:US20160028841A1

    公开(公告)日:2016-01-28

    申请号:US14806797

    申请日:2015-07-23

    CPC classification number: H04L67/26 H04L67/18 H04L67/42

    Abstract: A server is provided comprising a processor configured to: receive an indication of a location of a first device that is subscribed to a disaster notification service; in response to receiving a disaster alert, detect that the first device is located in an area associated with the disaster based on the indication of the location of the first device; identify a second device that has registered the first device as a friend; and transmit a first indication of the disaster to the first device and a second indication of the disaster to the second device.

    Abstract translation: 提供的服务器包括:处理器,其被配置为:接收订阅灾难通知服务的第一设备的位置的指示; 响应于接收到灾难警报,基于所述第一设备的位置的指示来检测所述第一设备位于与所述灾难相关联的区域中; 识别已将第一设备注册为朋友的第二设备; 并向第一设备发送灾难的第一指示,并向第二设备发送灾难的第二指示。

    APPARATUS FOR DISPLAYING THREE-DIMENSIONAL IMAGE
    7.
    发明申请
    APPARATUS FOR DISPLAYING THREE-DIMENSIONAL IMAGE 审中-公开
    显示三维图像的装置

    公开(公告)号:US20150177527A1

    公开(公告)日:2015-06-25

    申请号:US14577049

    申请日:2014-12-19

    Abstract: A three-dimensional (3D) image display device is provided. The 3D image display device comprises a first display panel, a second display panel spaced apart from the first display panel at a front side of the first display panel to display a three-dimensional (3D) image, and a spacing panel. A back surface of the spacing panel is coupled to the first display panel and a front surface thereof is coupled to the second display panel. As a result, a specific state in which a predetermined spacing between the first display panel and the second display panel is uniformly maintained through the spacing panel.

    Abstract translation: 提供三维(3D)图像显示装置。 3D图像显示装置包括第一显示面板,在第一显示面板的前侧与第一显示面板间隔开的第二显示面板,以显示三维(3D)图像和间隔面板。 间隔面板的后表面与第一显示面板连接,其前表面与第二显示面板连接。 结果,通过间隔板均匀地保持第一显示面板和第二显示面板之间的预定间隔的特定状态。

    BACKLIGHT UNIT AND DISPLAY DEVICE INCLUDING THE SAME
    9.
    发明申请
    BACKLIGHT UNIT AND DISPLAY DEVICE INCLUDING THE SAME 有权
    背光单元和包括其的显示装置

    公开(公告)号:US20140104877A1

    公开(公告)日:2014-04-17

    申请号:US14052137

    申请日:2013-10-11

    CPC classification number: G02B6/0031 F21V7/0025 G02B6/0088

    Abstract: A backlight unit includes a light guide plate; a light emitting unit configured to irradiate light toward a side portion of the light guide plate, the side portion comprising an upper side part and a lower side part; and a light controller of which at least a portion is in at least one from among the upper and the lower side parts of the side portion of the light guide plate. The light controller includes a first region overlapping the light guide plate and a second region not overlapping the light guide plate, and a reflectivity of the first region is different from a reflectivity of the second region.

    Abstract translation: 背光单元包括导光板; 发光单元,被配置为朝向所述导光板的侧部照射光,所述侧部包括上侧部和下侧部; 以及至少一部分在导光板的侧部的上侧部分和下侧部分中至少一部分的光控制器。 光控制器包括与导光板重叠的第一区域和不与导光板重叠的第二区域,并且第一区域的反射率不同于第二区域的反射率。

    POWER MANAGEMENT INTEGRATED CIRCUIT AND MEMORY MODULE INCLUDNG THE SAME

    公开(公告)号:US20250166692A1

    公开(公告)日:2025-05-22

    申请号:US18748051

    申请日:2024-06-19

    Abstract: A power management integrated circuit includes an internal output transistor connected to an external voltage input line, to which an external voltage is supplied, and outputting an internal output voltage, a self-overvoltage protection circuit detecting whether the external voltage exceeds a breakdown condition for the internal output transistor and providing a gate voltage to a gate terminal of the internal output transistor and a clamp circuit outputting, as the internal output voltage, a first clamp voltage having a uniform level in a first overvoltage clamp mode and a second clamp voltage, which is leveled down from the external voltage, in a second overvoltage clamp mode. When the internal output transistor is turned off, the clamp circuit outputs the internal output voltage. The external voltage in the second overvoltage clamp mode may be greater than the external voltage in the first overvoltage clamp mode.

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