公开(公告)号：US11023650B2

公开(公告)日：2021-06-01

申请号：US16663332

申请日：2019-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongda Lu ,  Kok-Hoong Chiu ,  Vaibhav Sharma

IPC: G06F30/398 ,  G06F30/3312 ,  G06F119/12 ,  G06F119/18 ,  G06F30/337 ,  G06F30/367 ,  G06F30/39

Abstract: A timing fixing logic section may select a timing path from among a plurality of timing paths. For the selected timing path, multiple nets along the path may be traversed. For a particular net, multiple metal layers may be traversed. For a particular metal layer, multiple shapes that are associated with the particular net may be traversed. A timing fixing logic section may examine space that is nearby each of the shapes, and identify unused space. The timing fixing logic section may add an extension metal section to the shape. In addition, the timing fixing logic section may identify an existing via of a first type, and select an alternate via of a second type having a resistance that is higher or lower than the existing via. The existing via may be replaced with the alternate via. Accordingly, hold and setup timing of a circuit may be improved.