公开(公告)号：US11023646B2

公开(公告)日：2021-06-01

申请号：US16664791

申请日：2019-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sridhar Subramaniam ,  Hongda Lu ,  Kok-Hoong Chiu

IPC: G06F1/10 ,  G06F30/396 ,  G06F1/08 ,  G06F30/30 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F30/3312 ,  G06F119/12

Abstract: A method of automatically constructing a hierarchical clock tree for an integrated circuit may include constructing a global clock tree on a first level based on first-level constraints, pushing the global clock tree to partitions on a second level, and generating second-level constraints for the partitions on the second level. The second-level constraints may be included in configuration files that may be generated for the partitions on the second level. The first-level constraints may be included in a first-level configuration file that is user-modifiable. The second-level constraints may include information for replicating multiple instantiated partitions on the second level. The method may further include modifying terminal names and/or configurations after pushdown. The method may further include creating infrastructure to analyze timing of the global clock tree.

公开(公告)号：US11748548B2

公开(公告)日：2023-09-05

申请号：US17573632

申请日：2022-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongda Lu ,  Sridhar Subramaniam ,  Kok-Hoong Chiu

IPC: G06F30/394 ,  G06F119/12

CPC classification number: G06F30/394 ,  G06F2119/12

Abstract: A method of constructing a hierarchical clock tree for an integrated circuit may include constructing a clock distribution network on a first level, pushing the clock distribution network to a second level, implementing partition clock trees in partitions on the second level, and calculating combined timing of the clock distribution network and the partition clock trees on the second level. Implementing the partition clock trees may include constructing the partition dock trees in the partitions on the second level, calculating trial timing for the partition clock trees, calculating target timing constraints for the partition clock trees based on timing of the dock distribution network and the trial timing for the partition dock trees, and adjusting the timing of one or more of the partition clock trees based on the target constraints.

公开(公告)号：US11023650B2

公开(公告)日：2021-06-01

申请号：US16663332

申请日：2019-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongda Lu ,  Kok-Hoong Chiu ,  Vaibhav Sharma

IPC: G06F30/398 ,  G06F30/3312 ,  G06F119/12 ,  G06F119/18 ,  G06F30/337 ,  G06F30/367 ,  G06F30/39

Abstract: A timing fixing logic section may select a timing path from among a plurality of timing paths. For the selected timing path, multiple nets along the path may be traversed. For a particular net, multiple metal layers may be traversed. For a particular metal layer, multiple shapes that are associated with the particular net may be traversed. A timing fixing logic section may examine space that is nearby each of the shapes, and identify unused space. The timing fixing logic section may add an extension metal section to the shape. In addition, the timing fixing logic section may identify an existing via of a first type, and select an alternate via of a second type having a resistance that is higher or lower than the existing via. The existing via may be replaced with the alternate via. Accordingly, hold and setup timing of a circuit may be improved.

公开(公告)号：US11263379B2

公开(公告)日：2022-03-01

申请号：US16666389

申请日：2019-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongda Lu ,  Sridhar Subramaniam ,  Kok-Hoong Chiu

IPC: G06F30/394 ,  G06F119/12

Abstract: A method of constructing a hierarchical clock tree for an integrated circuit may include constructing a clock distribution network on a first level, pushing the clock distribution network to a second level, implementing partition clock trees in partitions on the second level, and calculating combined timing of the clock distribution network and the partition clock trees on the second level. Implementing the partition clock trees may include constructing the partition clock trees in the partitions on the second level, calculating trial timing for the partition clock trees, calculating target timing constraints for the partition clock trees based on timing of the clock distribution network and the trial timing for the partition clock trees, and adjusting the timing of one or more of the partition clock trees based on the target constraints.

公开(公告)号：US11042678B2

公开(公告)日：2021-06-22

申请号：US16664792

申请日：2019-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naman Gupta ,  Vinayak Kini ,  Hongda Lu

IPC: G06F30/327 ,  G06K9/62 ,  G06N3/04 ,  G06F1/10 ,  G06F30/39 ,  G06F30/396

Abstract: A method for modeling clock gate timing for an integrated circuit may include creating a dataset having measured values of at least two design features and corresponding measured values of clock gate timing, applying an analytical framework to the dataset to determine how the design features affect the clock gate timing, measuring values of design features for a clock tree for the integrated circuit, and generating predicted values of clock gate timing for the clock tree for the integrated circuit based on how the design features of the dataset affect the clock gate timing of the dataset. The clock tree for the integrated circuit may be a second clock tree, and creating the dataset may include constructing a first clock tree, measuring values of design features of the first clock tree, and measuring corresponding values of clock gate timing of the first clock tree.