公开(公告)号：US11818531B2

公开(公告)日：2023-11-14

申请号：US17584888

申请日：2022-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Un Bang ,  Yong Hwan Kim ,  Arom Lee

IPC: H04R1/02 ,  H04R1/10

CPC classification number: H04R1/1025

Abstract: An electronic device that includes a first mobile device, and a second mobile device directly connected with the first mobile device through a power line, the second mobile device being configured to perform power line communication with the first mobile device through the power line for a first time period, and perform wireless communication with an external device for a second time period, the second time period not overlapping the first time period.

公开(公告)号：US10972080B2

公开(公告)日：2021-04-06

申请号：US16865502

申请日：2020-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Hwan Kim ,  Wook Kim ,  Ji Youn Kim

IPC: H03K3/03 ,  H03K3/011 ,  G06F1/08 ,  H03K19/00 ,  H03K19/003 ,  G06F1/324

Abstract: Clock generation and control in a semiconductor system having process, voltage and temperature (PVT) variation. A semiconductor device may include at least first and second ring oscillators, each disposed at locations respectively closest to first and second logic circuits of an operation circuit, and generating first and second oscillating signals. A detecting circuit is configured to perform a predetermined logic operation on the first oscillating signal and the second oscillating signal to generate a first clock signal. A calibration circuit is configured to receive the first clock signal from the detecting circuit and perform a delay control on each of the first ring oscillator and the second ring oscillator to generate a second clock signal for operating the operation circuit.

公开(公告)号：US12302053B2

公开(公告)日：2025-05-13

申请号：US18479730

申请日：2023-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Un Bang ,  Yong Hwan Kim ,  Arom Lee

IPC: H04R1/10

Abstract: An electronic device that includes a first mobile device, and a second mobile device directly connected with the first mobile device through a power line, the second mobile device being configured to perform power line communication with the first mobile device through the power line for a first time period, and perform wireless communication with an external device for a second time period, the second time period not overlapping the first time period.

公开(公告)号：US11201195B2

公开(公告)日：2021-12-14

申请号：US16052734

申请日：2018-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Won Hong ,  Yong Hwan Kim ,  Eui Jin Kim ,  Hak Yeol Kim ,  Jong Dae Park ,  Woo Young Oh ,  Su Jin Yun ,  Kwang Tai Kim ,  Hyung Sup Byeon ,  Su Cheol Cheong

IPC: H01L27/32 ,  G06F3/041 ,  H01L51/52 ,  H01L51/00 ,  G06F3/044

Abstract: An electronic device includes a first lead, a second lead, a touch sensitive display panel including a screen area and an extended area that extends from the screen area, and a control circuit. The touch sensitive display panel includes a flexible substrate, a thin film transistor (TFT) layer including a plurality of light-emitting elements, an insulation layer in which a via-hole is formed, and a touch sensor. The first lead is formed on the TFT layer in the screen area and the extended area and connects the control circuit and the plurality of light-emitting elements. The second lead is formed on the insulation layer in the screen area and on the TFT layer in the extended area, and extends from the screen area to the extended area through the via-hole formed in the insulation layer and connects the control circuit and the touch sensor.

公开(公告)号：US10659014B2

公开(公告)日：2020-05-19

申请号：US15988064

申请日：2018-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong Hwan Kim ,  Wook Kim ,  Ji Youn Kim

IPC: H03K3/03 ,  H03K3/011 ,  G06F1/08 ,  H03K19/00 ,  H03K19/003 ,  G06F1/324

Abstract: Clock generation and control in a semiconductor system having process, voltage and temperature (PVT) variation. A semiconductor device may include at least first and second ring oscillators, each disposed at locations respectively closest to first and second logic circuits of an operation circuit, and generating first and second oscillating signals. A detecting circuit is configured to perform a predetermined logic operation on the first oscillating signal and the second oscillating signal to generate a first clock signal. A calibration circuit is configured to receive the first clock signal from the detecting circuit and perform a delay control on each of the first ring oscillator and the second ring oscillator to generate a second clock signal for operating the operation circuit.