公开(公告)号：US20220406935A1

公开(公告)日：2022-12-22

申请号：US17584580

申请日：2022-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongsung WOO ,  Changmin JEON ,  Yongkyu LEE

IPC: H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a gate structure, source and drain regions, and first and second lightly doped drain (LDD) regions. The source and drain regions are spaced apart and formed in an active region of the substrate at opposite sides of the gate structure. The first LDD region surrounds one side surface and a bottom surface of the drain region and has a first junction depth. The second LDD region surrounds one side surface and a bottom surface of the source region and has a second junction depth less than the first junction depth. The gate structure includes a gate dielectric layer, a gate electrode, and gate spacers respectively disposed on opposite side walls of the gate dielectric layer and the gate electrode. One side wall of the gate dielectric layer and electrode is aligned with one side surface of the first LDD region.

公开(公告)号：US20230035568A1

公开(公告)日：2023-02-02

申请号：US17725993

申请日：2022-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyongsik YEOM ,  Changmin JEON ,  Yongkyu LEE

IPC: H01L27/1157

Abstract: A memory device includes a first bit line configured to supply a first bit line bias voltage, a memory cell transistor having a first operating voltage, a selection transistor having a second operating voltage and configured to control the supply of the first bit line bias voltage to a source of the memory cell transistor, and a second bit line connected to a drain of the memory cell transistor. A level of the first operating voltage is about equal to a level of the second operating voltage.

公开(公告)号：US20190259437A1

公开(公告)日：2019-08-22

申请号：US16285295

申请日：2019-02-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boyoung SEO ,  Seongui SEO ,  Gwanhyeob KOH ,  Yongkyu LEE

IPC: G11C11/16 ,  H01L27/22

Abstract: A magnetic memory device includes a substrate, a landing pad on the substrate, first and second magnetic tunnel junction patterns disposed on the interlayer insulating layer and spaced apart from the landing pad when viewed from a plan view, and an interconnection structure electrically connecting a top surface of the second magnetic tunnel junction pattern to the landing pad. A distance between the landing pad and the first magnetic tunnel junction pattern is greater than a distance between the first and second magnetic tunnel junction patterns, and a distance between the landing pad and the second magnetic tunnel junction pattern is greater than the distance between the first and second magnetic tunnel junction patterns, when viewed from a plan view.