公开(公告)号：US12158772B2

公开(公告)日：2024-12-03

申请号：US18170747

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongun Jeong ,  Donghyeok Jeong ,  ChangSik Yoo ,  Kihan Kim

IPC: G06F1/12

Abstract: Disclosed is a clock multiplexing circuit which includes a first transistor that is between a first input terminal that receives a first input clock signal and an output terminal that outputs an output pulse signal and operates based on a logic level of a second input terminal receiving a second input clock signal, and a second transistor that is between the output terminal and a first voltage node and operates based on the logic level of the second input terminal. The first input clock signal and the second input clock signal have the same period and have different phases. The output pulse signal transitions to a first logic level at a first time when the first input clock signal transitions to the first logic level and transitions to a second logic level at a second time when the second input clock signal transitions to the first logic level.

公开(公告)号：US20250044828A1

公开(公告)日：2025-02-06

申请号：US18922797

申请日：2024-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongun Jeong ,  Donghyeok Jeong ,  ChangSik Yoo ,  Kihan Kim

IPC: G06F1/12

Abstract: Disclosed is a clock multiplexing circuit which includes a first transistor that is between a first input terminal that receives a first input clock signal and an output terminal that outputs an output pulse signal and operates based on a logic level of a second input terminal receiving a second input clock signal, and a second transistor that is between the output terminal and a first voltage node and operates based on the logic level of the second input terminal. The first input clock signal and the second input clock signal have the same period and have different phases. The output pulse signal transitions to a first logic level at a first time when the first input clock signal transitions to the first logic level and transitions to a second logic level at a second time when the second input clock signal transitions to the first logic level.

公开(公告)号：US20240028065A1

公开(公告)日：2024-01-25

申请号：US18170747

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongun Jeong ,  Donghyeok Jeong ,  ChangSik Yoo ,  Kihan Kim

IPC: G06F1/12

CPC classification number: G06F1/12

Abstract: Disclosed is a clock multiplexing circuit which includes a first transistor that is between a first input terminal that receives a first input clock signal and an output terminal that outputs an output pulse signal and operates based on a logic level of a second input terminal receiving a second input clock signal, and a second transistor that is between the output terminal and a first voltage node and operates based on the logic level of the second input terminal. The first input clock signal and the second input clock signal have the same period and have different phases. The output pulse signal transitions to a first logic level at a first time when the first input clock signal transitions to the first logic level and transitions to a second logic level at a second time when the second input clock signal transitions to the first logic level.