公开(公告)号：US12158772B2

公开(公告)日：2024-12-03

申请号：US18170747

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongun Jeong ,  Donghyeok Jeong ,  ChangSik Yoo ,  Kihan Kim

IPC: G06F1/12

Abstract: Disclosed is a clock multiplexing circuit which includes a first transistor that is between a first input terminal that receives a first input clock signal and an output terminal that outputs an output pulse signal and operates based on a logic level of a second input terminal receiving a second input clock signal, and a second transistor that is between the output terminal and a first voltage node and operates based on the logic level of the second input terminal. The first input clock signal and the second input clock signal have the same period and have different phases. The output pulse signal transitions to a first logic level at a first time when the first input clock signal transitions to the first logic level and transitions to a second logic level at a second time when the second input clock signal transitions to the first logic level.

公开(公告)号：US20230377667A1

公开(公告)日：2023-11-23

申请号：US18319584

申请日：2023-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewoo Lee ,  Yonghun Kim ,  Kihan Kim ,  ChangSik Yoo

IPC: G11C29/12 ,  G11C29/36

CPC classification number: G11C29/12015 ,  G11C29/36 ,  G11C29/1201

Abstract: A semiconductor device includes: a data clock signal generator circuit configured to output a plurality of data clock signals that have different phases and that are used to generate a plurality of internal data clock signals of a memory device; a data transmitter configured to generate a data signal based on a test pattern transitioned once, delay the data signal once transitioned according to a delay value, and output the data signal to the memory device; a data receiver configured to receive an output signal from the memory device that includes first sampling data, the first sampling data being obtained by sampling the data signal based on a first internal data clock signal from the plurality of internal data clock signals; and a training circuit configured to change the delay value and determine a final value of the delay value based on the first sampling data.

公开(公告)号：US20250006233A1

公开(公告)日：2025-01-02

申请号：US18885337

申请日：2024-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghun Lee ,  Kiho Kim ,  Kihan Kim

IPC: G11C7/10

Abstract: Disclosed are a memory device that performs offset calibration and a method of operating the memory device. The memory device includes an input/output pad configured to receive data from a device external, an on-die termination (ODT) circuit connected to the input/output pad, a plurality of receivers connected to the ODT circuit and configured to receive the data from the input/output pad, an offset calibration circuit configured to perform an offset calibration operation on data output from the plurality of receivers and output an offset correction, a first switch configured to provide a first voltage to the plurality of receivers, and a second switch configured to provide a second voltage to the plurality of receivers. During the offset calibration operation, the plurality of receivers receive a third voltage in response to the ODT circuit being enabled and the first voltage through the first switch.

公开(公告)号：US20240212725A1

公开(公告)日：2024-06-27

申请号：US18468227

申请日：2023-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Garam Choi ,  Yonghun Kim ,  Kihan Kim

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C2207/2254

Abstract: Provided are a memory device and a method for training per-pin operation parameters. A memory device includes a plurality of on-die termination (ODT) circuits, an impedance control (ZQ) calibration circuit configured to output a first code signal and a second code signal, and a per-pin calibration circuit. The per-pin calibration circuit may be configured to select one signal pin from among the plurality of signal pins, to compare a first input voltage level of the selected signal pin with a second input voltage level of each of the other ones of the plurality of signal pins, to generate a per-pin ODT code signal for each of the plurality of signal pins, to combine the per-pin ODT code signal with the first code signal or the second code signal, and to provide the combined per-pin ODT code signal to the respective ODT circuits.

公开(公告)号：US20240119997A1

公开(公告)日：2024-04-11

申请号：US18221598

申请日：2023-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： GARAM CHOI ,  Yonghun Kim ,  Jaewoo Lee ,  Kihan Kim ,  Hojun Chang

IPC: G11C11/4093 ,  G11C11/4074 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G11C11/4074 ,  G11C11/4076

Abstract: A semiconductor chip includes a write clock buffer, a voltage regulator, a process calibration circuit and a temperature calibration circuit. The voltage regulator generates plural regulated voltages. The process calibration circuit output one of the regulated voltages as a bias voltage of the write clock buffer, depending on a process variation of the semiconductor chip. The temperature calibration circuit track a temperature variation of the semiconductor chip in real time, performs analog calibration on the bias voltage from the process calibration circuit in real time depending on a result of the tracking, and outputs the analog-calibrated bias voltage to the write clock buffer.

公开(公告)号：US20230377621A1

公开(公告)日：2023-11-23

申请号：US18189580

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewoo Lee ,  Yonghun Kim ,  Kihan Kim ,  ChangSik Yoo

IPC: G11C7/22 ,  G11C7/10 ,  G11C29/02

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C29/023 ,  G11C7/1093 ,  G11C2207/2254

Abstract: A semiconductor device includes: a clock generation circuit configured to output a plurality of clock signals that have different phases to a memory device, an internal clock signal of the memory device being generated responsive to the plurality of clock signals; and a training circuit configured to receive an output signal output based on the internal clock signal from the memory device, to adjust a value of a code used to generate the internal clock signal by adjusting the phase of at least one clock signal among the plurality of clock signals, to determine a final value of the code based on a duty cycle of the output signal, which is changed according to the adjustment of the value of the code, and to write the final value to the memory device.

公开(公告)号：US20230129949A1

公开(公告)日：2023-04-27

申请号：US17968052

申请日：2022-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghun Lee ,  Kiho Kim ,  Kihan Kim

IPC: G11C7/10

Abstract: Disclosed are a memory device that performs offset calibration and a method of operating the memory device. The memory device includes an input/output pad configured to receive data from a device external, an on-die termination (ODT) circuit connected to the input/output pad, a plurality of receivers connected to the ODT circuit and configured to receive the data from the input/output pad, an offset calibration circuit configured to perform an offset calibration operation on data output from the plurality of receivers and output an offset correction, a first switch configured to provide a first voltage to the plurality of receivers, and a second switch configured to provide a second voltage to the plurality of receivers. During the offset calibration operation, the plurality of receivers receive a third voltage in response to the ODT circuit being enabled and the first voltage through the first switch.

公开(公告)号：US20240028065A1

公开(公告)日：2024-01-25

申请号：US18170747

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongun Jeong ,  Donghyeok Jeong ,  ChangSik Yoo ,  Kihan Kim

IPC: G06F1/12

CPC classification number: G06F1/12

Abstract: Disclosed is a clock multiplexing circuit which includes a first transistor that is between a first input terminal that receives a first input clock signal and an output terminal that outputs an output pulse signal and operates based on a logic level of a second input terminal receiving a second input clock signal, and a second transistor that is between the output terminal and a first voltage node and operates based on the logic level of the second input terminal. The first input clock signal and the second input clock signal have the same period and have different phases. The output pulse signal transitions to a first logic level at a first time when the first input clock signal transitions to the first logic level and transitions to a second logic level at a second time when the second input clock signal transitions to the first logic level.

公开(公告)号：US20250044828A1

公开(公告)日：2025-02-06

申请号：US18922797

申请日：2024-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongun Jeong ,  Donghyeok Jeong ,  ChangSik Yoo ,  Kihan Kim

IPC: G06F1/12

Abstract: Disclosed is a clock multiplexing circuit which includes a first transistor that is between a first input terminal that receives a first input clock signal and an output terminal that outputs an output pulse signal and operates based on a logic level of a second input terminal receiving a second input clock signal, and a second transistor that is between the output terminal and a first voltage node and operates based on the logic level of the second input terminal. The first input clock signal and the second input clock signal have the same period and have different phases. The output pulse signal transitions to a first logic level at a first time when the first input clock signal transitions to the first logic level and transitions to a second logic level at a second time when the second input clock signal transitions to the first logic level.

公开(公告)号：US12125553B2

公开(公告)日：2024-10-22

申请号：US17968052

申请日：2022-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghun Lee ,  Kiho Kim ,  Kihan Kim

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C7/1084 ,  G11C2207/2254

Abstract: Disclosed are a memory device that performs offset calibration and a method of operating the memory device. The memory device includes an input/output pad configured to receive data from a device external, an on-die termination (ODT) circuit connected to the input/output pad, a plurality of receivers connected to the ODT circuit and configured to receive the data from the input/output pad, an offset calibration circuit configured to perform an offset calibration operation on data output from the plurality of receivers and output an offset correction, a first switch configured to provide a first voltage to the plurality of receivers, and a second switch configured to provide a second voltage to the plurality of receivers. During the offset calibration operation, the plurality of receivers receive a third voltage in response to the ODT circuit being enabled and the first voltage through the first switch.