公开(公告)号：US20250006641A1

公开(公告)日：2025-01-02

申请号：US18405023

申请日：2024-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Hee KANG ,  Jong Min BAEK ,  Eui Bok LEE

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device including a first interlayer insulating layer on a substrate, a lower wiring pattern in the first interlayer insulating layer, a second interlayer insulating layer on the first interlayer insulating layer, a via filling layer filling a via trench in the second interlayer insulating layer, a third interlayer insulating layer contacting an upper surface of the second interlayer insulating layer, and an upper wiring pattern in an upper wiring trench formed on the via trench in the third interlayer insulating layer and contacting an upper surface of the via filling layer, the upper wiring pattern including a first upper wiring barrier layer on sidewalls of the upper wiring trench, a second upper wiring barrier layer on sidewalls of the first upper wiring barrier layer and the upper surface of the via filling layer, and an upper wiring filling layer on the second upper wiring barrier layer.