公开(公告)号：US20240120274A1

公开(公告)日：2024-04-11

申请号：US18217012

申请日：2023-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok LEE ,  Rak Hwan KIM ,  Jong Min BAEK ,  Moon Kyun SONG

IPC: H01L23/522 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L21/823475 ,  H01L23/5283 ,  H01L27/088

Abstract: A semiconductor device a first fin-shaped pattern provided at a first surface of a substrate and extending in a second direction, a first source/drain pattern disposed on the first fin-shaped pattern and connected thereto, a first source/drain contact disposed on the first source/drain pattern and connected thereto, a buried conductive pattern extending through the substrate and connected to the first source/drain contact, a contact connection via disposed between the first source/drain contact and the buried conductive pattern. The contact connection via is directly connected to the first source/drain contact and a back wiring line disposed on a second surface of the substrate and connected to the buried conductive pattern. A width of the contact connection via increases as the contact connection via extends away from the second surface. A width of the first source/drain contact decreases as the first source/drain contact extends away from the second surface of the substrate.

公开(公告)号：US20170213786A1

公开(公告)日：2017-07-27

申请号：US15333508

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon AHN ,  Tae Soo KIM ,  Jong Min BAEK ,  Woo Kyung YOU ,  Thomas OSZINDA ,  Byung Hee KIM ,  Nae In LEE

IPC: H01L23/498 ,  H01L23/535

CPC classification number: H01L23/53295 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.

公开(公告)号：US20240112949A1

公开(公告)日：2024-04-04

申请号：US18537896

申请日：2023-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jin KANG ,  Jong Min BAEK ,  Woo Kyung YOU ,  Kyu-Hee HAN ,  Han Seong KIM ,  Jang Ho LEE ,  Sang Shin JANG

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76808 ,  H01L23/481 ,  H01L21/76832

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

公开(公告)号：US20210020497A1

公开(公告)日：2021-01-21

申请号：US16798789

申请日：2020-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Jin KANG ,  Jong Min BAEK ,  Woo Kyung YOU ,  Kyu-Hee HAN ,  Han Seong KIM ,  Jang Ho LEE ,  Sang Shin JANG

IPC: H01L21/768 ,  H01L23/48

Abstract: A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

公开(公告)号：US20190181088A1

公开(公告)日：2019-06-13

申请号：US16039838

申请日：2018-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Deok Young JUNG ,  Sang Bom KANG ,  Doo-Hwan PARK ,  Jong Min BAEK ,  Sang Hoon AHN ,  Hyeok Sang OH ,  Woo Kyung YOU

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer. The first insulating film and the second insulating film may be sequentially stacked on the substrate in a vertical direction, and a longest vertical distance between an upper surface of the lower metal layer and the substrate may be less than a longest vertical distance between the upper surface of the second insulating film and the substrate.

公开(公告)号：US20190148289A1

公开(公告)日：2019-05-16

申请号：US15987211

申请日：2018-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon Seok SEO ,  Jong Min BAEK ,  Su Hyun BARK ,  Sang Hoon AHN ,  Hyeok Sang OH ,  Eui Bok LEE

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.

公开(公告)号：US20250006641A1

公开(公告)日：2025-01-02

申请号：US18405023

申请日：2024-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Hee KANG ,  Jong Min BAEK ,  Eui Bok LEE

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device including a first interlayer insulating layer on a substrate, a lower wiring pattern in the first interlayer insulating layer, a second interlayer insulating layer on the first interlayer insulating layer, a via filling layer filling a via trench in the second interlayer insulating layer, a third interlayer insulating layer contacting an upper surface of the second interlayer insulating layer, and an upper wiring pattern in an upper wiring trench formed on the via trench in the third interlayer insulating layer and contacting an upper surface of the via filling layer, the upper wiring pattern including a first upper wiring barrier layer on sidewalls of the upper wiring trench, a second upper wiring barrier layer on sidewalls of the first upper wiring barrier layer and the upper surface of the via filling layer, and an upper wiring filling layer on the second upper wiring barrier layer.

公开(公告)号：US20230411498A1

公开(公告)日：2023-12-21

申请号：US18175821

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Hee HAN ,  Bong Kwan BAEK ,  Sang Shin JANG ,  Koung Min RYU ,  Jong Min BAEK ,  Jung Hoo SHIN ,  Jun Hyuk LIM ,  Jung Hwan CHUN

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/66795 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475

Abstract: A method for fabricating semiconductor device may include forming a source/drain pattern on a fin-type pattern, forming an etch stop film and an interlayer insulating film on the source/drain pattern, forming a contact hole in the interlayer insulating film, forming a sacrificial liner along a sidewall and a bottom surface of the contact hole, performing an ion implantation process while the sacrificial liner is present, removing the sacrificial liner and forming a contact liner along the sidewall of the contact hole, and forming a source/drain contact on the contact liner. The ion implantation process may include implant impurities into the source/drain pattern. The source/drain contact may be connected to the source/drain pattern.

公开(公告)号：US20190043803A1

公开(公告)日：2019-02-07

申请号：US15840128

申请日：2017-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Kyung YOU ,  Eui Bok LEE ,  Jong Min BAEK ,  Su Hyun BARK ,  Jang Ho LEE ,  Sang Hoon AHN ,  Hyeok Sang OH

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.

公开(公告)号：US20190019759A1

公开(公告)日：2019-01-17

申请号：US16135234

申请日：2018-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hoon AHN ,  Tae Soo KIM ,  Jong Min BAEK ,  Woo Kyung YOU ,  Thomas OSZINDA ,  Byung Hee KIM ,  Nae In LEE

IPC: H01L23/532

Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.