公开(公告)号：US12218096B2

公开(公告)日：2025-02-04

申请号：US17707007

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongkwon Ko ,  Unbyoung Kang ,  Soyeon Kwon ,  Yoonsung Kim ,  Teakhoon Lee

IPC: H01L23/544 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes: a semiconductor substrate having a front side and a back side, the semiconductor substrate having a chip area and a dummy area; a front structure below the front side, and including an internal circuit, an internal connection pattern, a guard pattern, and a front insulating structure; a rear protective layer overlapping the chip area and the dummy area, and a rear protrusion pattern on the rear protective layer and overlapping the dummy area, the rear protective layer and the rear protrusion pattern being on the back side; a through-electrode structure penetrating through the chip area and the rear protective layer, and electrically connected to the internal connection pattern; and a rear pad electrically connected to the through-electrode structure. The internal circuit and the internal connection pattern are below the chip area, and the guard pattern is below the chip area adjacent to the dummy area.

公开(公告)号：US20230086202A1

公开(公告)日：2023-03-23

申请号：US17839675

申请日：2022-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang ,  Yoonsung Kim ,  Seungduk Baek ,  Yunrae Cho

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/66

Abstract: A semiconductor package is provided. The semiconductor package includes, a base structure including a body, an upper pad on the body, and an upper insulating layer on a side surface of the upper pad, the base structure having a planar upper surface provided by the upper insulating layer and the upper pad; and a semiconductor chip on the planar upper surface of the base structure, and including a substrate, a wiring structure below the substrate, a low dielectric layer on a side surface of the wiring structure, a lower connection pad below the wiring structure, and a lower insulating layer on a side surface of the lower connection pad, the semiconductor chip having a planar lower surface provided by the lower insulating layer and the lower connection pad, a side surface provided by the lower insulating layer and the substrate, and a recess surface extending from one end of the side surface to one end of the planar lower surface, wherein the low dielectric layer is spaced apart from the recess surface of the semiconductor chip by the lower insulating layer.