公开(公告)号：US20250096088A1

公开(公告)日：2025-03-20

申请号：US18966239

申请日：2024-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/18

Abstract: A semiconductor package includes a base substrate; an interposer substrate including a semiconductor substrate having a first surface facing the base substrate and a second surface, opposing the first surface, and a passivation layer on at least a portion of the first surface; a plurality of connection bumps between the base substrate and the interposer substrate; an underfill resin in a space between the base substrate and the interposer substrate; and a first semiconductor chip and a second semiconductor chip on the interposer substrate. The interposer substrate has a first region, in which the plurality of connection bumps are included, and a second region and a third region adjacent a periphery of the first region, and the passivation layer is in the second region and includes a first embossed pattern in the second region.

公开(公告)号：US20230207528A1

公开(公告)日：2023-06-29

申请号：US18117601

申请日：2023-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/481 ,  H01L25/0652 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2225/06544 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A semiconductor package comprising a first semiconductor chip and a second semiconductor chip disposed on the first semiconductor chip, wherein the first semiconductor chip includes a first semiconductor body, an upper pad structure, and a first through-electrode penetrating the first semiconductor body and electrically connected to the upper pad structure, and the second semiconductor chip includes a second semiconductor body, a lower bonding pad, and an internal circuit structure including a circuit element, internal circuit wirings, and a connection pad pattern disposed on the same level as the lower bonding pad, the upper pad structure includes upper bonding pads and connection wirings, the upper bonding pads are disposed at positions corresponding to the lower bonding pad and the connection pad pattern, and the internal circuit structure is electrically connected to the first through-electrode through at least one of the upper bonding pads and the connection wirings.

公开(公告)号：US20250069972A1

公开(公告)日：2025-02-27

申请号：US18658652

申请日：2024-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haseob Seong ,  Seungduk Baek ,  Aenee Jang

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: Provided is a semiconductor package including a first semiconductor chip including a first semiconductor substrate having an active surface and an inactive surface opposite to each other, a plurality of second semiconductor chips each including a second semiconductor substrate having an active surface and an inactive surface opposite to each other, and a package molding layer including a bottom molding portion on a portion of an upper surface of the first semiconductor chip, which is exposed by the lowermost second semiconductor chip, and a side molding portion on side walls of the plurality of second semiconductor chips, wherein the side molding portion of the package molding layer extends in a vertical direction from an edge of an upper surface of the bottom molding portion of the package molding layer.

公开(公告)号：US11581234B2

公开(公告)日：2023-02-14

申请号：US16888990

申请日：2020-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younglyong Kim ,  Myungkee Chung ,  Aenee Jang

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/31

Abstract: A semiconductor package including a semiconductor chip, an interposer on the semiconductor chip, and a molding layer covering at least a portion of the semiconductor chip and at least a portion of the interposer may be provided. The interposer includes a interposer substrate and a heat dissipation pattern penetrating the interposer substrate and electrically insulated from the semiconductor chip. The heat dissipation pattern includes a through electrode disposed in the interposer substrate and an upper pad disposed on an upper surface of the interposer substrate and connected to the through electrode. The molding layer covers at least a portion of a sidewall of the upper pad and the upper surface of the interposer substrate. At least a portion of an upper surface of the upper pad is not covered by the molding layer.

公开(公告)号：US20250167156A1

公开(公告)日：2025-05-22

申请号：US19028917

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang ,  Younglyong Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate having first and second surfaces opposite to each other, a through electrode in the first substrate, a first chip pad on the first surface and electrically connected to the through electrode, and a second chip pad on the first surface and electrically connected to a circuit element in the first substrate; a redistribution wiring layer on the first surface of the first semiconductor chip, and including a first redistribution wiring line electrically connected to the first chip pad and a second redistribution wiring line electrically connected to the second chip pad; a second semiconductor chip stacked on the second surface of the first semiconductor chip and electrically connected to the through electrode; and a molding member on side surfaces of the first and second semiconductor chips.

公开(公告)号：US20240047389A1

公开(公告)日：2024-02-08

申请号：US18141675

申请日：2023-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonmin Lee ,  Jihoon Kim ,  Aenee Jang

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L24/80 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0657 ,  H01L24/08 ,  H01L24/06 ,  H01L2924/1431 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/95001 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1434 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2224/80203 ,  H01L2224/08145 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06133 ,  H01L2224/05007 ,  H01L2224/05187 ,  H01L2224/05124 ,  H01L2224/05647 ,  H01L2224/05015 ,  H01L2224/05018 ,  H01L2224/05082 ,  H01L2224/05541 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05687

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of first pads disposed on a front surface of the first substrate, a first insulating layer surrounding the plurality of first pads, and a plurality of wiring patterns disposed between the first substrate and the plurality of first pads and electrically connected to the plurality of first pads; and a second semiconductor chip disposed below the first semiconductor chip and including a second substrate, a plurality of second pads disposed on the second substrate and contacting the plurality of first pads, a second insulating layer surrounding the plurality of second pads and contacting the first insulating layer, and a plurality of through-electrodes penetrating through the second substrate to be connected to the plurality of second pads. The plurality of wiring patterns include top wiring patterns adjacent to the plurality of first pads in a direction perpendicular to the front surface. On a plane parallel to the front surface, within a first region having a first shape and first region area from a top down view, first top wiring patterns have a first occupied area between adjacent first pads of a first group of first pads from among the plurality of first pads, and within a second region having the first shape and first region area from a top down view, second top wiring patterns have a second occupied area, larger than the first occupied area, between adjacent first pads of a second group of first pads from among the plurality of first pads. From a top down view, each pad of the first group of first pads has a first area, and each pad of the second group of first pads has a second area, wherein the first area is smaller than a second area.

公开(公告)号：US20230187329A1

公开(公告)日：2023-06-15

申请号：US18167369

申请日：2023-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/3171 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/05 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238

Abstract: A semiconductor package includes a base substrate; an interposer substrate including a semiconductor substrate having a first surface facing the base substrate and a second surface, opposing the first surface, and a passivation layer on at least a portion of the first surface; a plurality of connection bumps between the base substrate and the interposer substrate; an underfill resin in a space between the base substrate and the interposer substrate; and a first semiconductor chip and a second semiconductor chip on the interposer substrate. The interposer substrate has a first region, in which the plurality of connection bumps are included, and a second region and a third region adjacent a periphery of the first region, and the passivation layer is in the second region and includes a first embossed pattern in the second region.

公开(公告)号：US11594516B2

公开(公告)日：2023-02-28

申请号：US17245978

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer and spaced apart from each other, and electrically connected to each other through the interposer, at least one dummy member on the interposer to cover at least one corner portion of the interposer and arranged spaced apart from a first semiconductor device among the plurality of semiconductor devices, and a sealing member contacting the interposer and filling a space between the first semiconductor device and the at least one dummy member so as to cover a first side surface of the first semiconductor device, a first side surface of the at least one dummy member, and an upper surface of the dummy member. A second side surface, opposite to the first side surface, of the at least one dummy member is uncovered by the sealing member.

公开(公告)号：US20220068881A1

公开(公告)日：2022-03-03

申请号：US17245978

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer and spaced apart from each other, and electrically connected to each other through the interposer, at least one dummy member on the interposer to cover at least one corner portion of the interposer and arranged spaced apart from a first semiconductor device among the plurality of semiconductor devices, and a sealing member contacting the interposer and filling a space between the first semiconductor device and the at least one dummy member so as to cover a first side surface of the first semiconductor device, a first side surface of the at least one dummy member, and an upper surface of the dummy member. A second side surface, opposite to the first side surface, of the at least one dummy member is uncovered by the sealing member.

公开(公告)号：US12237290B2

公开(公告)日：2025-02-25

申请号：US16912819

申请日：2020-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Aenee Jang ,  Younglyong Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate having first and second surfaces opposite to each other, a through electrode in the first substrate, a first chip pad on the first surface and electrically connected to the through electrode, and a second chip pad on the first surface and electrically connected to a circuit element in the first substrate; a redistribution wiring layer on the first surface of the first semiconductor chip, and including a first redistribution wiring line electrically connected to the first chip pad and a second redistribution wiring line electrically connected to the second chip pad; a second semiconductor chip stacked on the second surface of the first semiconductor chip and electrically connected to the through electrode; and a molding member on side surfaces of the first and second semiconductor chips.