公开(公告)号：US20250147920A1

公开(公告)日：2025-05-08

申请号：US18756924

申请日：2024-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moongyung KIM ,  Euiyeon WON ,  Donghyeon HAM ,  Youngsik EOM ,  Ara CHO

IPC: G06F15/80 ,  G06F9/48

Abstract: A multi-core processor according to some example embodiments may be a multi-core processor including a plurality of cores, and may include a first core that receives a task migration instruction, and transmits metadata including branch prediction data obtained during execution of a migration subject task determined as a subject of the task migration instruction among a plurality of tasks, to an external memory, and a second core that receives a task execution instruction, and reads the metadata from the external memory on the basis of the task execution instruction, and executes the migration subject task using the metadata.

公开(公告)号：US20240320152A1

公开(公告)日：2024-09-26

申请号：US18607858

申请日：2024-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moongyung KIM ,  Euiyeon WON ,  Donghyeon HAM ,  Youngsik EOM ,  Ara CHO

IPC: G06F12/0811

CPC classification number: G06F12/0811

Abstract: An electronic device including a main memory, a plurality of caches that are hierarchically connected, the plurality of caches configured to store part of data stored in the main memory, and processing circuitry configured to transmit a memory request for desired data to the plurality of caches and the main memory, the memory request including cache allocation range information associated with the desired data, and each of the plurality of caches are configured to, determine whether to perform an operation corresponding to the memory request based on the cache allocation range information.