公开(公告)号：US20240143540A1

公开(公告)日：2024-05-02

申请号：US18494152

申请日：2023-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moongyung KIM

IPC: G06F15/78 ,  G06F1/08

CPC classification number: G06F15/7814 ,  G06F1/08

Abstract: A system on chip (SoC) includes a processor configured to execute code corresponding to at least one application and a performance controller configured to generate control information for controlling performance of the processor for each function to be executed by the processor by using a history table in which a plurality of history performance information items respectively corresponding to a plurality of functions included in the code are stored and to generate a control signal corresponding to the control information.

公开(公告)号：US20240193120A1

公开(公告)日：2024-06-13

申请号：US18502551

申请日：2023-11-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moongyung KIM

IPC: G06F15/78 ,  G06F11/34

CPC classification number: G06F15/7807 ,  G06F11/3495

Abstract: Disclosed are system-on-chip devices (SoCs) and operating methods thereof. A system-on-chip (SOC) may include a memory including a history storage, a processor configured to execute an application, performance optimization module configured to generate and transmit optimized control information for the processor executing a function included in the application, based on a history corresponding to the function, when the processor executes the function and the history corresponding to the function is in the history storage, and a performance management module configured to generate a control signal for controlling performance of the processor, based on the optimized control information received from the performance optimization module, wherein the history includes control information for the processor and utilization information accumulated according to the control information, the control information having been accumulated during at least one time of previous execution of the function.

公开(公告)号：US20250147920A1

公开(公告)日：2025-05-08

申请号：US18756924

申请日：2024-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moongyung KIM ,  Euiyeon WON ,  Donghyeon HAM ,  Youngsik EOM ,  Ara CHO

IPC: G06F15/80 ,  G06F9/48

Abstract: A multi-core processor according to some example embodiments may be a multi-core processor including a plurality of cores, and may include a first core that receives a task migration instruction, and transmits metadata including branch prediction data obtained during execution of a migration subject task determined as a subject of the task migration instruction among a plurality of tasks, to an external memory, and a second core that receives a task execution instruction, and reads the metadata from the external memory on the basis of the task execution instruction, and executes the migration subject task using the metadata.

公开(公告)号：US20240143061A1

公开(公告)日：2024-05-02

申请号：US18494104

申请日：2023-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moongyung KIM

IPC: G06F1/324 ,  G06F1/08 ,  G06F1/3228

CPC classification number: G06F1/324 ,  G06F1/08 ,  G06F1/3228

Abstract: A system-on-chip includes a processor configured to execute code corresponding to at least one application and a throttling controller configured to generate throttling control information by using a history table storing a plurality of pieces of history utilization information respectively corresponding to a plurality of functions included in the code, the throttling control information controlling throttling of the processor with respect to each of the plurality of functions, and generate a throttling control signal corresponding to the throttling control information.

公开(公告)号：US20240320152A1

公开(公告)日：2024-09-26

申请号：US18607858

申请日：2024-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moongyung KIM ,  Euiyeon WON ,  Donghyeon HAM ,  Youngsik EOM ,  Ara CHO

IPC: G06F12/0811

CPC classification number: G06F12/0811

Abstract: An electronic device including a main memory, a plurality of caches that are hierarchically connected, the plurality of caches configured to store part of data stored in the main memory, and processing circuitry configured to transmit a memory request for desired data to the plurality of caches and the main memory, the memory request including cache allocation range information associated with the desired data, and each of the plurality of caches are configured to, determine whether to perform an operation corresponding to the memory request based on the cache allocation range information.

公开(公告)号：US20240193067A1

公开(公告)日：2024-06-13

申请号：US18534262

申请日：2023-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moongyung KIM

IPC: G06F11/34

CPC classification number: G06F11/3409

Abstract: A system on chip includes a processor configured to execute an application by using a shared library, the application being supported by an operating system, a performance prediction module configured to generate control information of the processor for executing a function by the processor and predictive performance information of the processor that is predicted during control according to the control information when the function included in the shared library is executed the control information referencing a history corresponding to the function from a history table, and a performance management module configured to generate a control signal for performance control of the processor based on the control information, wherein the history is an accumulation of performance information of the processor measured by executing in advance the function at least once.

公开(公告)号：US20230152990A1

公开(公告)日：2023-05-18

申请号：US17987551

申请日：2022-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moongyung KIM

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0629 ,  G06F3/0683

Abstract: A system on chip is provided. The system on chip includes: a plurality of memory controllers respectively connected to a plurality of memory devices; a plurality of logic circuits, each logic circuit being configured to perform a data processing operation using at least one of the plurality of memory controllers; and a bus connection interface configured to select a first hash function from among a plurality of hash functions based on a first address region corresponding to first addresses received from a first logic circuit from among the plurality of logic circuits, obtain hashed first addresses by applying the first hash function to the first addresses, and connect at least one of the plurality of memory controllers to the first logic circuit using a first access method that corresponds to the hashed first addresses.