公开(公告)号：US20230152976A1

公开(公告)日：2023-05-18

申请号：US17986021

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhyun Kim ,  Taeeun Park ,  Yukyeong Kim ,  Yejin Shin ,  Donggeun Lim ,  Seonghoon Woo

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0653 ,  G06F3/0679

Abstract: A memory system may include a plurality of first memory devices; and a memory controller that may include a first chip enable (CE) pin configured to output a first CE signal that enables selectively any one of the first memory devices and a first status input pin configured to receive a first output signal indicating a memory operation status of an enabled first memory device from among the first memory devices in a first memory operation status checking period. In the first memory operation status checking period, the first output signal has one of a first level to indicate a first status of the memory operation status of the enabled first memory device, a second level to indicate a second status of the memory operation status of the enabled first memory device, or a third level to indicate a disabled status of the first memory devices.