公开(公告)号：US10936003B1

公开(公告)日：2021-03-02

申请号：US15803672

申请日：2017-11-03

Applicant: Seagate Technology LLC

Inventor： Zheng Wu ,  Jason Bellorado ,  Marcus Marrow ,  Trung Thuc Nguyen ,  Wing Fai Hui ,  Kin Ming Chan

IPC: G06F1/08 ,  G06F1/12 ,  H03L7/07 ,  H03L7/093 ,  H03L7/095

Abstract: Systems and methods are disclosed for phase locking multiple clocks of different frequencies. In certain embodiments, an apparatus may be configured to downsample a first clock having a first frequency and a second clock having a second frequency into downsampled clocks having the same frequency. The apparatus may adjust a frequency of the second clock so that the downsampled clocks are phase aligned. The apparatus may reset counters of the divider circuits that perform the downsampling so align them to a counter for the first clock. A counter for the second clock may also be reset to align with the counter for the first clock. The synchronized clocks may be applied in data storage operations, such as self-servo writing operations, where the first clock may be a read clock and the second clock may be a write clock.