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公开(公告)号：US20220247418A1
公开(公告)日：2022-08-04
申请号：US17582376
申请日：2022-01-24
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
Abstract: Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.
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公开(公告)号：US11336304B2
公开(公告)日：2022-05-17
申请号：US16908593
申请日：2020-06-22
Applicant: Seagate Technology LLC
Inventor： Deepak Sridhara , Jason Bellorado , Ara Patapoutian , Marcus Marrow
Abstract: In one implementation, the disclosure provides a decoding system that concurrently executes a read sample combining recovery process and an iterative outer code (IOC) recovery process. Performing the read sample combining recovery process entails executing multiple rounds of logic that each provide for combining together different data samples read from a data block. The IOC recovery process is performed at least partially concurrent with the read sample combining recovery process and each round of the IOC recovery process is based on newly-updated data samples generated by the read sample combining recovery process.
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公开(公告)号：US11018842B1
公开(公告)日：2021-05-25
申请号：US16051252
申请日：2018-07-31
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
Abstract: An apparatus may include a sampling circuit configured to produce a sequence of input samples based on a continuous time input signal and a sample clock signal, the sampling phase of the sequence of input samples based on a phase control value output by a timing recovery circuit. In addition, the apparatus may include the timing recovery circuit configured to receive the sequence of input samples, detect, for a current sample of the sequence of input samples, a phase offset in the sampling phase of the sequence of input samples, the phase offset being a deviation of the sampling phase from an expected phase, and in response to detecting the phase offset, select a bandwidth for timing recovery. Further, the timing recovery circuit may generate an updated phase control value based on the selected bandwidth for timing recovery.
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公开(公告)号：US10755734B2
公开(公告)日：2020-08-25
申请号：US16570785
申请日：2019-09-13
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
IPC: G11B5/596 , G11B20/10 , H04L25/03 , G06F13/10 , G06F13/42 , H03K5/131 , H03M1/00 , H03M13/41 , H03K5/135 , H03L7/07 , H03L7/081 , H03L7/091 , H03G3/20 , H03M1/12 , H04L7/00 , H03M13/29 , H04B1/7105 , H03K5/00 , H04L7/033
Abstract: An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.
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公开(公告)号：US10665256B2
公开(公告)日：2020-05-26
申请号：US15791190
申请日：2017-10-23
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
IPC: G11B5/596 , G11B20/10 , H04L25/03 , H03K5/131 , H03M1/00 , H03M13/41 , H03K5/135 , H03L7/07 , H03L7/081 , H03L7/091 , H04L7/00 , H03M13/29 , H04B1/7105 , H03K5/00 , H04L7/033
Abstract: An apparatus may include a circuit configured to receive a first phase control value of a phase control value signal, generate a first phase interpolator control signal value of a phase interpolator control signal and generate a first digital interpolator control signal value of a digital interpolator control signal. The apparatus may further be configured to phase interpolate a clock signal based on the first phase interpolator control signal value to produce a phase shifted clock signal and digitally interpolate a digital sample based on the first digital interpolator signal value to produce a phase shifted digital sample having an effective phase based on the first phase control value, the digital sample generated using the phase shifted clock signal as a sample clock.
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Patent Agency Ranking
公开(公告)号：US20200005819A1
公开(公告)日：2020-01-02
申请号：US16570785
申请日：2019-09-13
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
IPC: G11B5/596 , H03L7/091 , H03M1/00 , G11B20/10 , H03L7/081 , H03L7/07 , H03K5/131 , H03K5/135 , H03M13/41
Abstract: An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.
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公开(公告)号：US10277718B1
公开(公告)日：2019-04-30
申请号：US15359591
申请日：2016-11-22
Applicant: Seagate Technology LLC
Inventor： Jason Vincent Bellorado , Marcus Marrow
Abstract: Systems and methods are disclosed for detection and mitigation of defects within a preamble portion of a signal, such as a data sector preamble recorded to a data storage medium. In certain embodiments, an apparatus may comprise a circuit configured to synchronize a sampling phase for sampling a signal pattern. The circuit may sample a preamble field of the signal pattern to obtain sample values, split the sample values into a plurality of groups, determine defect groups having samples corresponding to defects in the preamble field, remove the defect groups from the plurality of groups, and synchronize the sampling phase based on the plurality of groups.
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公开(公告)号：US10243703B1
公开(公告)日：2019-03-26
申请号：US15810545
申请日：2017-11-13
Applicant: Seagate Technology LLC
Inventor： Jason Vincent Bellorado , Marcus Marrow
IPC: H04L1/20 , H04L12/801 , H04W84/12
Abstract: Systems and methods are disclosed for detection of a selected signal pattern, such as a servo sector preamble, and for frequency offset determination. A circuit may be configured to divide a signal into detection windows of a selected size, and sample the signal a selected number of times within each detection window. The circuit may then determine an error value for each detection window based on values of the samples for each detection window, and determine the preamble is detected when a threshold number of most-recently sampled detection windows have error values below a threshold value. The circuit may then organize the sample values corresponding to the preamble into groups, and calculate phase estimates representing a phase at which the groups were sampled. The circuit may determine a frequency offset based on the phase estimates, and modulate the sampling frequency according to the frequency offset.
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公开(公告)号：US09979573B1
公开(公告)日：2018-05-22
申请号：US15390447
申请日：2016-12-23
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Jason Vincent Bellorado , Trung Thuc Nguyen
Abstract: A method may generate a demodulated sine component for a sequence of samples of a servo burst window of a position error signal using a sine weight look up table and generate a demodulated cosine component for the sequence of samples of the servo burst window of the position error signal using a cosine weight look up table. The sine weight and the cosine weight look up tables may have indexes representing a phase range. The method may generate a demodulated phase component signal and a demodulated amplitude component signal for the sequence of samples of the servo burst window of the position error signal based on the demodulated sine component and the demodulated cosine component using a Coordinate Rotation Digital Computer at least in part by iteratively rotating a vector based on the demodulated sine component and the demodulated cosine component and summing angular changes in the vector.
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公开(公告)号：US11900970B2
公开(公告)日：2024-02-13
申请号：US17162218
申请日：2021-01-29
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
CPC classification number: G11B5/09 , G06F13/385 , H03M1/12 , G11B2005/0013
Abstract: Systems and methods are disclosed for magnetoresistive asymmetry compensation using a hybrid analog and digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing, via the CTFE circuit, first magnetoresistive asymmetry (MRA) compensation on the analog signal to adjust the dynamic range of the analog signal based on an input range of an analog-to-digital converter (ADC). The method may further comprise converting the analog signal to a digital sample sequence via the ADC, and performing, via a digital MRA compensation circuit, second MRA compensation to correct residual MRA in the digital sample sequence. Offset compensation may also be performed in both the analog and digital domains.
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