公开(公告)号：US11595058B1

公开(公告)日：2023-02-28

申请号：US17733724

申请日：2022-04-29

Applicant: Seagate Technology LLC

Inventor： Naveen Kumar ,  Shuhei Tanakamaru ,  Erich Franz Haratsch

IPC: H03M13/01 ,  H03M13/11 ,  H03M13/39

Abstract: Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.

公开(公告)号：US20210328597A1

公开(公告)日：2021-10-21

申请号：US16849491

申请日：2020-04-15

Applicant: Seagate Technology LLC

Inventor： Naveen Kumar ,  Shuhei Tanakamaru ,  Erich Franz Haratsch

IPC: H03M13/01 ,  H03M13/11 ,  H03M13/39

Abstract: Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.

公开(公告)号：US10354699B1

公开(公告)日：2019-07-16

申请号：US16000581

申请日：2018-06-05

Applicant: Seagate Technology LLC

Inventor： Shankar Gopalakrishna ,  Anil Koyad Choyikkunnil ,  Saju Cheeran Verghese Francis ,  Naveen Kumar

IPC: G06F1/18 ,  G11B33/12

Abstract: A storage chassis may be adapted, or configured, to secure a plurality of carrierless devices (e.g., without the use of a carrier or drive tray) received thereby. The storage chassis may include a base, a first drive wall coupled to and extending from the base, and a second drive wall coupled to and extending from the base. Each of the first and second drive walls may include a top edge spaced away from a bottom portion of the base. The base, the first drive wall, and the second drive wall may define a row of drive slots and each drive slot may be configured to receive a carrierless device. Further, the storage chassis may include a plurality of locking units configured to extend across corresponding drive slots between the top edge of the first drive wall and the top edge of the second drive wall.

公开(公告)号：US11349495B2

公开(公告)日：2022-05-31

申请号：US16849491

申请日：2020-04-15

Applicant: Seagate Technology LLC

Inventor： Naveen Kumar ,  Shuhei Tanakamaru ,  Erich Franz Haratsch

IPC: H03M13/01 ,  H03M13/39 ,  H03M13/11

Abstract: Hard errors are determined for an unsuccessful decoding of codeword bits read from NAND memory cells via a read channel and input to a low-density parity check (LDPC) decoder. A bit error rate (BER) for the hard errors is estimated and BER for the read channel is estimated. Hard error regions are found using a single level cell (SLC) reading of the NAND memory cells. A log likelihood ratio (LLR) mapping of the codeword bits input to the LDPC decoder is changed based on the hard error regions, the hard error BER, and/or the read channel BER.