公开(公告)号：US20190121740A1

公开(公告)日：2019-04-25

申请号：US15790297

申请日：2017-10-23

Applicant: Seagate Technology LLC

Inventor： Nitin Satishchandra Kabra ,  Sidheshkumar Ramanlal Patel ,  Sneha Kishor Wagh

IPC: G06F12/0868 ,  G06F3/06 ,  G06F12/02 ,  G06F15/78 ,  G06F5/06 ,  G06F12/0873 ,  G06F12/1027 ,  G06F12/1009

Abstract: A cache management mechanism is provided having a size that is independent of an overall storage capacity of a non-volatile memory (NVM). The cache management mechanism includes a first level map data structure arranged as a first-in-first-out (FIFO) buffer to list a plurality of host access commands sequentially received from a host device. Each command has an associated host tag value. A cache memory stores user data blocks associated with the commands. A second level map of the cache management mechanism correlates cache addresses with the host tag values. A processing core searches the FIFO buffer in an effort to match a logical address of an existing command to the logical address for a new command. If a match is found, the host tag value is used to locate the cache address for the requested data. If a cache miss occurs, the new command is forwarded to the NVM.

公开(公告)号：US11232037B2

公开(公告)日：2022-01-25

申请号：US15790297

申请日：2017-10-23

Applicant: Seagate Technology LLC

Inventor： Nitin Satishchandra Kabra ,  Sidheshkumar Ramanlal Patel ,  Sneha Kishor Wagh

IPC: G06F12/0868 ,  G06F3/06 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/1027

Abstract: A cache management mechanism is provided having a size that is independent of an overall storage capacity of a non-volatile memory (NVM). The cache management mechanism includes a first level map data structure arranged as a first-in-first-out (FIFO) buffer to list a plurality of host access commands sequentially received from a host device. Each command has an associated host tag value. A cache memory stores user data blocks associated with the commands. A second level map of the cache management mechanism correlates cache addresses with the host tag values. A processing core searches the FIFO buffer in an effort to match a logical address of an existing command to the logical address for a new command. If a match is found, the host tag value is used to locate the cache address for the requested data. If a cache miss occurs, the new command is forwarded to the NVM.

公开(公告)号：US11025678B2

公开(公告)日：2021-06-01

申请号：US15879982

申请日：2018-01-25

Applicant: Seagate Technology LLC

Inventor： Sneha Kishor Wagh ,  Siddharth Shirish Suttraway

IPC: G06F15/16 ,  H04L29/06 ,  G06F9/38 ,  G06F3/06

Abstract: Implementations described and claimed herein provide methods and systems for routing data, message, and register access transactions through common ports in an on-chip interface interconnect module while supporting Quality of Service (QoS) and maintaining fair data throughput. In one implementation, a System on Chip system includes an AXI interconnect module to route data, message, and register access transactions via common ports in the AXI interconnect module. The system may include at least one master circuit module configured to initiate data transaction, wherein the at least one master circuit module behaves as a slave to receive message transactions and register access transactions. The system may include at least one slave circuit module configured to respond to data transactions, wherein the at least one slave circuit module behaves as a master to initiate message transactions. The system may use QoS signaling as a priority indicator to prioritize the transactions.