公开(公告)号：US11025678B2

公开(公告)日：2021-06-01

申请号：US15879982

申请日：2018-01-25

Applicant: Seagate Technology LLC

Inventor： Sneha Kishor Wagh ,  Siddharth Shirish Suttraway

IPC: G06F15/16 ,  H04L29/06 ,  G06F9/38 ,  G06F3/06

Abstract: Implementations described and claimed herein provide methods and systems for routing data, message, and register access transactions through common ports in an on-chip interface interconnect module while supporting Quality of Service (QoS) and maintaining fair data throughput. In one implementation, a System on Chip system includes an AXI interconnect module to route data, message, and register access transactions via common ports in the AXI interconnect module. The system may include at least one master circuit module configured to initiate data transaction, wherein the at least one master circuit module behaves as a slave to receive message transactions and register access transactions. The system may include at least one slave circuit module configured to respond to data transactions, wherein the at least one slave circuit module behaves as a master to initiate message transactions. The system may use QoS signaling as a priority indicator to prioritize the transactions.