公开(公告)号：US20190351982A1

公开(公告)日：2019-11-21

申请号：US16352444

申请日：2019-03-13

Applicant: Seong Jae LEE ,  HWASEUNG EXWILL CO., LTD.

Inventor： Soon Hwan YUN ,  Young Chun KIM ,  Seong Jae LEE

IPC: B63B59/02

Abstract: Disclosed is a shut-off valve installed in an accommodation chamber regulating entry/exit of air. The shut-off valve includes: a body removably disposed in the accommodation chamber and having multiple air passage holes; a valve stem adapted to be moved vertically along a valve stem insertion hole formed in the body; a disc mounted on a disc engagement portion formed at a lower end of the valve stem to open/close at least one of the multiple air passage holes; a rotor disposed on an upper side of the body to vertically move the valve stem, the rotor being provided with an opening/closing indicator to check opening/closing of the shut-off valve outside the accommodation chamber, wherein the accommodation chamber has an upper wall, a lower wall, and a side wall, the body disposed passing through the upper wall and lower wall of the accommodation chamber, and the disc is located outside the accommodation chamber.

公开(公告)号：US20090215232A1

公开(公告)日：2009-08-27

申请号：US12434779

申请日：2009-05-04

Applicant: Yark Yeon KIM ,  Seong Jae LEE ,  Moon Gyu JANG ,  Chel Jong CHOI ,  Myung Sim JUN ,  Byoung Chul PARK

Inventor： Yark Yeon KIM ,  Seong Jae LEE ,  Moon Gyu JANG ,  Chel Jong CHOI ,  Myung Sim JUN ,  Byoung Chul PARK

IPC: H01L21/338

CPC classification number: H01L29/47 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/7839

Abstract: Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.

Abstract translation: 提供了一种肖特基势垒隧道晶体管及其制造方法，该晶体管能够使用在半导体 - 金属结上自然形成的肖特基隧道势垒作为隧道来最小化对肖特基势垒隧道晶体管的栅极侧壁的损坏所造成的漏电流 屏障。 该方法包括以下步骤：在绝缘基板上形成半导体沟道层; 在半导体沟道层上形成虚拟栅极; 在绝缘基板上的虚拟栅极的两侧形成源极和漏极; 去除虚拟门; 在去除所述伪栅极的侧壁上形成绝缘层; 并且在从其中去除虚拟栅极的空间中形成实际栅极。 在使用伪栅极制造肖特基势垒隧道晶体管时，可以形成高k电介质栅极绝缘层和金属栅极，并且可以获得具有非常强反应性的金属层的硅化物的稳定特性。

公开(公告)号：US20110228613A1

公开(公告)日：2011-09-22

申请号：US13118287

申请日：2011-05-27

Applicant: Seong Jae LEE

Inventor： Seong Jae LEE

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4093

Abstract: A method is provided for achieving SRAM output characteristics from DRAMs, in which a plurality of DRAMs are arranged connected in parallel to a controller in such a way as to be able to obtain SRAM output characteristics using the DRAMs, comprising a process in which data is output to an external device when a control signal for data reading has been input from the external device, by sequentially repeating a step in which the controller sends a data output state control signal to one DRAM and sends a refresh standby state control signal to the other DRAMs, the data is read and sent to the external device from the DRAM in the output state, and a refresh standby state control signal is sent to the DRAM which was in the output state while an output state control signal is sent to another DRAM and data is read out from the DRAM in the output state, and a step in which the controller sends a control signal for changing the output state to the refresh standby state.

Abstract translation: 提供了一种用于实现DRAM的SRAM输出特性的方法，其中以能够使用DRAM获得SRAM输出特性的方式将多个DRAM并行连接到控制器的方式，包括数据为 当从外部设备输入用于数据读取的控制信号时，通过依次重复控制器向一个DRAM发送数据输出状态控制信号并向另一个DRAM发送刷新待机状态控制信号的步骤，将其输出到外部设备 DRAM，在输出状态下从DRAM读取数据并将其发送到外部设备，并且将刷新待机状态控制信号发送到处于输出状态的DRAM，同时将输出状态控制信号发送到另一个DRAM， 在输出状态下从DRAM中读出数据，并且控制器将用于将输出状态改变为刷新待机状态的控制信号的步骤。