公开(公告)号：US07352228B2

公开(公告)日：2008-04-01

申请号：US11416608

申请日：2006-05-03

申请人： Shahid Ali ,  Sujan Manohar ,  Satheesh Balasubramanian

发明人： Shahid Ali ,  Sujan Manohar ,  Satheesh Balasubramanian

IPC分类号： H03L5/00

CPC分类号： H03K19/018521 ,  H03K19/00323 ,  H03K19/01721

摘要： A method and/or a system of control signal synchronization of a scannable storage circuit is disclosed. In one embodiment, a system includes a first circuit to operate based on a first voltage of a first power supply, a second circuit to operate based on a second voltage of a second power supply, a level shifter circuit between the first circuit and the second circuit to translate between the first voltage of the first power supply and the second voltage of the second power supply, and a n-channel metal-oxide semiconductor field-effect transistor (nMOSFET) having a gate input of the second voltage and serially coupled in a fall path of the level shifter circuit to increase a rate of a capacitive discharge such that the rate of a capacitive discharge charge is substantially equal to a rate of a capacitive charge (e.g., the fall delay may also increase a bit because of an extra transistor).

摘要翻译： 公开了一种具有占空比校正的电平移位电路的方法和装置。 在一个实施例中，系统包括基于第一电源的第一电压操作的第一电路，基于第二电源的第二电压进行操作的第二电路，第一电路和第二电源之间的电平移位器电路 在第一电源的第一电压和第二电源的第二电压之间平移的电路以及具有第二电压的栅极输入并串联耦合的n沟道金属氧化物半导体场效应晶体管（nMOSFET） 电平移位器电路的下降路径，以增加电容放电的速率，使得电容放电电荷的速率基本上等于容性电荷的速率（例如，由于额外的额外的下降延迟也可能增加一点 晶体管）。

公开(公告)号：US20070257722A1

公开(公告)日：2007-11-08

申请号：US11416608

申请日：2006-05-03

申请人： Shahid Ali ,  Sujan Manohar ,  Satheesh Balasubramanian

发明人： Shahid Ali ,  Sujan Manohar ,  Satheesh Balasubramanian

IPC分类号： H03L5/00

CPC分类号： H03K19/018521 ,  H03K19/00323 ,  H03K19/01721

摘要： A method and/or a system of control signal synchronization of a scannable storage circuit is disclosed. In one embodiment, a system includes a first circuit to operate based on a first voltage of a first power supply, a second circuit to operate based on a second voltage of a second power supply, a level shifter circuit between the first circuit and the second circuit to translate between the first voltage of the first power supply and the second voltage of the second power supply, and a n-channel metal-oxide semiconductor field-effect transistor (nMOSFET) having a gate input of the second voltage and serially coupled in a fall path of the level shifter circuit to increase a rate of a capacitive discharge such that the rate of a capacitive discharge charge is substantially equal to a rate of a capacitive charge (e.g., the fall delay may also increase a bit because of an extra transistor).

摘要翻译： 公开了一种可扫描存储电路的控制信号同步的方法和/或系统。 在一个实施例中，系统包括基于第一电源的第一电压操作的第一电路，基于第二电源的第二电压进行操作的第二电路，第一电路和第二电源之间的电平移位器电路 在第一电源的第一电压和第二电源的第二电压之间平移的电路以及具有第二电压的栅极输入并串联耦合的n沟道金属氧化物半导体场效应晶体管（nMOSFET） 电平移位器电路的下降路径，以增加电容放电的速率，使得电容放电电荷的速率基本上等于容性电荷的速率（例如，由于额外的额外的下降延迟也可能增加一点 晶体管）。

公开(公告)号：US20100019825A1

公开(公告)日：2010-01-28

申请号：US12179616

申请日：2008-07-25

申请人： Shahid Ali ,  Sujan Manohar

发明人： Shahid Ali ,  Sujan Manohar

IPC分类号： H03L5/00

CPC分类号： H03K19/018521

摘要： A method, system, and apparatus to a novel single supply level shifter circuit for multi-voltage designs, capable of up/down shifting are disclosed. In one embodiment, a system includes a first circuit, a second circuit, a voltage source with an output voltage equal to a voltage value of the second circuit, a level shifter circuit coupled with both an output of the first circuit and an output of the voltage source and wherein the level shifter circuit is used to convert a voltage value of a signal from the first circuit to the voltage value of the second circuit, and a capacitor loop circuit associated with the first circuit, the level shifter circuit and the voltage source and configured with a capacitor to charge from at least one of a first circuit output voltage.

摘要翻译： 公开了一种用于多电压设计的新型单电源电平移位电路的方法，系统和装置，其能够上/下移位。 在一个实施例中，系统包括第一电路，第二电路，具有等于第二电路的电压值的输出电压的电压源，与第一电路的输出和第一电路的输出耦合的电平移位器电路 电压源，其中电平移位器电路用于将来自第一电路的信号的电压值转换为第二电路的电压值，以及与第一电路，电平移位器电路和电压源相关联的电容器回路电路 并配置有电容器以从第一电路输出电压中的至少一个充电。

公开(公告)号：US07750717B2

公开(公告)日：2010-07-06

申请号：US12179616

申请日：2008-07-25

申请人： Shahid Ali ,  Sujan Manohar

发明人： Shahid Ali ,  Sujan Manohar

IPC分类号： H03L5/00

CPC分类号： H03K19/018521

摘要： A method, system, and apparatus to a novel single supply level shifter circuit for multi-voltage designs, capable of up/down shifting are disclosed. In one embodiment, a system includes a first circuit, a second circuit, a voltage source with an output voltage equal to a voltage value of the second circuit, a level shifter circuit coupled with both an output of the first circuit and an output of the voltage source and wherein the level shifter circuit is used to convert a voltage value of a signal from the first circuit to the voltage value of the second circuit, and a capacitor loop circuit associated with the first circuit, the level shifter circuit and the voltage source and configured with a capacitor to charge from at least one of a first circuit output voltage.

摘要翻译： 公开了一种用于多电压设计的新型单电源电平移位电路的方法，系统和装置，其能够上/下移位。 在一个实施例中，系统包括第一电路，第二电路，具有等于第二电路的电压值的输出电压的电压源，与第一电路的输出和第一电路的输出耦合的电平移位器电路 电压源，其中电平移位器电路用于将来自第一电路的信号的电压值转换为第二电路的电压值，以及与第一电路，电平移位器电路和电压源相关联的电容器回路电路 并配置有电容器以从第一电路输出电压中的至少一个充电。

公开(公告)号：US20070273420A1

公开(公告)日：2007-11-29

申请号：US11419766

申请日：2006-05-23

申请人： Pavan Vithal Torvi ,  Sujan Manohar

发明人： Pavan Vithal Torvi ,  Sujan Manohar

IPC分类号： H03K3/289

CPC分类号： H03K3/3562

摘要： A flip-flop is configured for low standby/leakage power for power-conservation, especially in battery operated portable devices using flip-flops. The flip-flop uses a clock and may be a D flip-flop, including a master latch with first and second inverters and a slave latch. The inverters in the master-latch are configured to be selectively gated. The gating is preferably done by first and second transistors receiving the clock signal and connected between a voltage source and the ground. The gating cuts off power supply to the inverters when the clock is low and reduces leakage power. The slave latch includes a primary inverter and a feedback inverter. Expediently, a transmission gate between the master-latch and the slave-latch is eliminated. The primary inverter in the slave-latch is not gated to prevent the input of the feedback inverter from going into a “floating” state.

摘要翻译： 触发器配置为用于节电的低待机/漏电功率，特别是在使用触发器的电池供电的便携式设备中。 触发器使用时钟并且可以是D触发器，包括具有第一和第二反相器的主锁存器和从锁存器。 主锁存器中的反相器配置为选择性门控。 门控优选地由接收时钟信号并连接在电压源和地之间的第一和第二晶体管完成。 当时钟低电平时门控器切断逆变器的电源，并减少漏电功率。 从锁存器包括主逆变器和反馈逆变器。 有利地，消除了主锁存器和从锁存器之间的传输门。 从锁存器中的主逆变器不是门控，以防止反馈逆变器的输入进入“浮动”状态。