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    LEVEL SHIFTER HAVING CURRENT BOOSTING STAGES
    1.
    发明公开
    LEVEL SHIFTER HAVING CURRENT BOOSTING STAGES 审中-公开

    公开(公告)号：US20240364340A1

    公开(公告)日：2024-10-31

    申请号：US18627941

    申请日：2024-04-05

    申请人： STMicroelectronics International N.V.

    发明人： Manoj Kumar TIWARI ,  Kailash KUMAR

    IPC分类号： H03K19/0185

    CPC分类号： H03K19/018521

    摘要： A level shifter having current boosting stages is provided. The level shifter includes a level shifting stage including a plurality of transistors and first and second nodes. The level shifting stage is configured to transfer a first signal of a first voltage domain to a second signal of a second voltage domain. A plurality of current boosting stages are associated with the transistors, respectively. A first current boosting stage provides a first boosting stage current path to support a first level shifter current path of a first transistor of the plurality of transistors in response to: a first supply voltage of the first voltage domain being greater than a second supply voltage of the second voltage domain, the first signal having a first logical state and the first node having a logical state reflecting that the first signal has a second logical state different from the first logical state.

    INTERFACE DEVICE AND DYNAMIC TRACKING BIAS CIRCUIT
    2.
    发明公开
    INTERFACE DEVICE AND DYNAMIC TRACKING BIAS CIRCUIT 审中-公开

    公开(公告)号：US20240364339A1

    公开(公告)日：2024-10-31

    申请号：US18615088

    申请日：2024-03-25

    申请人： MEDIATEK INC.

    发明人： Yu-Shen LIN ,  Jui-Ming CHEN ,  Federico Agustin ALTOLAGUIRRE

    IPC分类号： H03K19/0185 ,  H03K17/08

    CPC分类号： H03K19/018521 ,  H03K17/08

    摘要： An interface device includes a dynamic tracking bias circuit, an ESD (Electrostatic Discharge) clamp circuit, a pre-driver, a post-driver, and an I/O (Input/Output) pad. The dynamic tracking bias circuit provides a first supply voltage. The first supply voltage is determined according to a main power voltage and a second supply voltage. The ESD clamp circuit limits the second supply voltage. The post-driver is driven by the pre-driver. The I/O pad is driven by the post-driver. The pre-driver and the post-driver are supplied by the main power voltage, the first supply voltage, and the second supply voltage.

    Output buffer circuit
    7.
    发明授权
    Output buffer circuit 有权

    公开(公告)号：US12047068B2

    公开(公告)日：2024-07-23

    申请号：US18080378

    申请日：2022-12-13

    申请人： GlobalFoundries U.S. Inc.

    发明人： Dzung T. Tran ,  Shivraj G. Dharne

    IPC分类号： H03K19/01 ,  H03K19/003 ,  H03K19/0185

    CPC分类号： H03K19/018521 ,  H03K19/00315 ,  H03K19/00361

    摘要： The present disclosure relates to a structure including a level shifter circuit which receives an input signal and at least one voltage reference signal and outputs at least one level shifted output signal, a pre-driver circuit which receives the at least one level shifted output signal and outputs at least one pre-driver output signal, the pre-driver circuit including at least one delay circuit, and a main driver circuit which receives the at least one pre-driver output signal and outputs a main driver output signal.

    ENHANCED RISING AND FALLING TRANSITIONS FOR LEVEL SHIFTING LOW-VOLTAGE INPUT SIGNALS
    8.
    发明公开
    ENHANCED RISING AND FALLING TRANSITIONS FOR LEVEL SHIFTING LOW-VOLTAGE INPUT SIGNALS 审中-公开

    公开(公告)号：US20240235552A9

    公开(公告)日：2024-07-11

    申请号：US17970519

    申请日：2022-10-20

    申请人： QUALCOMM Incorporated

    发明人： Xu ZHANG ,  Xuhao HUANG

    IPC分类号： H03K19/0185 ,  H03K3/037

    CPC分类号： H03K19/018521 ,  H03K3/037 ,  H04M1/026

    摘要： A level-shifter is provided with a first transistor and a second transistor. The first transistor functions to discharge an internal node responsive to an assertion of an inverted input signal to a first power supply voltage. A second transistor functions to discharge an inverted level-shifter output signal responsive to an assertion of an input signal to the first power supply voltage. An inverter inverts the inverted level-shifter output signal to form a level-shifter output signal that is asserted to a second power supply voltage responsive to the assertion of the input signal.