公开(公告)号：US11868693B2

公开(公告)日：2024-01-09

申请号：US17236606

申请日：2021-04-21

Applicant: Siemens Industry Software Inc.

Inventor： Rohit Kumar Jain ,  David Lowder ,  James Insley ,  Srinivasa Cherukumilli

IPC: G06F30/33 ,  G06F16/23 ,  G06F111/02

CPC classification number: G06F30/33 ,  G06F16/2379 ,  G06F2111/02

Abstract: This application discloses a computing system implementing a design verification tool to perform functional verification on a circuit design describing an electronic device and collect samples of performance data during the functional verification. The computing system can also include a performance visualization tool to generate a profile presentation based on the samples of performance data. The profile presentation, when displayed, can annunciate portions of the circuit design corresponding to at least one performance hotspot. The performance visualization tool can receive a data reduction request based on the performance hotspot annunciated by the profile presentation. The data reduction request can identify a subset of the performance data in the profile presentation. The performance visualization tool can generate a refined profile presentation based, at least in part, on the samples of performance data and the subset of the performance data identified in the data reduction request.

公开(公告)号：US20230048929A1

公开(公告)日：2023-02-16

申请号：US17398070

申请日：2021-08-10

Applicant: Siemens Industry Software Inc.

Inventor： Rohit Kumar Jain ,  Jayvant Padmanabha Anantpur ,  Devon J. Kehoe ,  Vikas Sangal

IPC: G06F30/3312 ,  G06F30/398 ,  G06F30/337 ,  G06F30/3323

Abstract: A simulator can simulate a circuit design describing an electronic device using a single processing device of a computing system. The simulator can generate profile data associated with compilation of the circuit design and the single processing device simulation of the compiled circuit design. The profile data can identify multiple different ways to partition the circuit design and include information corresponding to the single processing device simulation of the compiled circuit design. A parallel simulation qualifier can determine a parallelism factor corresponding to an expected performance of the computing system in a multiple processing device simulation of the circuit design based on the profile data from the single processing device simulation of the circuit design. The simulator can utilize the parallelism factor to partition the circuit design in one of the different ways, and simulate the partitioned circuit design with multiple processing devices of the computing system.

公开(公告)号：US20220343044A1

公开(公告)日：2022-10-27

申请号：US17236606

申请日：2021-04-21

Applicant: Siemens Industry Software Inc.

Inventor： Rohit Kumar Jain ,  David Lowder ,  James Insley ,  Srinivasa Cherukumilli

IPC: G06F30/33 ,  G06F16/23

Abstract: This application discloses a computing system implementing a design verification tool to perform functional verification on a circuit design describing an electronic device and collect samples of performance data during the functional verification. The computing system can also include a performance visualization tool to generate a profile presentation based on the samples of performance data. The profile presentation, when displayed, can annunciate portions of the circuit design corresponding to at least one performance hotspot. The performance visualization tool can receive a data reduction request based on the performance hotspot annunciated by the profile presentation. The data reduction request can identify a subset of the performance data in the profile presentation. The performance visualization tool can generate a refined profile presentation based, at least in part, on the samples of performance data and the subset of the performance data identified in the data reduction request.