公开(公告)号：US10158354B2

公开(公告)日：2018-12-18

申请号：US15429690

申请日：2017-02-10

Applicant: Silicon Laboratories Inc.

Inventor： Arnab Kumar Dutta ,  Essam Atalla ,  Nicholas M. Atkinson

IPC: H03K17/61 ,  H03K17/16

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry that includes a pull-up network coupled to a supply voltage and at least one input signal. The IC further includes a first metal oxide semiconductor (MOS) transistor coupled to the pull-up network and to a first bias voltage to reduce a gate-induced drain leakage (GIDL) current of the CMOS circuitry.

公开(公告)号：US20190123734A1

公开(公告)日：2019-04-25

申请号：US16221552

申请日：2018-12-16

Applicant: Silicon Laboratories Inc.

Inventor： Arnab Kumar Dutta ,  Essam Atalla ,  Nicholas M. Atkinson

IPC: H03K17/16

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry that includes a pull-up network coupled to a supply voltage and at least one input signal. The IC further includes a first metal oxide semiconductor (MOS) transistor coupled to the pull-up network and to a first bias voltage to reduce a gate-induced drain leakage (GIDL) current of the CMOS circuitry.

公开(公告)号：US20180234089A1

公开(公告)日：2018-08-16

申请号：US15429690

申请日：2017-02-10

Applicant: Silicon Laboratories Inc.

Inventor： Arnab Kumar Dutta ,  Essam Atalla ,  Nicholas M. Atkinson

IPC: H03K17/16

CPC classification number: H03K17/161 ,  H03K2217/0036

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry that includes a pull-up network coupled to a supply voltage and at least one input signal. The IC further includes a first metal oxide semiconductor (MOS) transistor coupled to the pull-up network and to a first bias voltage to reduce a gate-induced drain leakage (GIDL) current of the CMOS circuitry.