公开(公告)号：US10158354B2

公开(公告)日：2018-12-18

申请号：US15429690

申请日：2017-02-10

Applicant: Silicon Laboratories Inc.

Inventor： Arnab Kumar Dutta ,  Essam Atalla ,  Nicholas M. Atkinson

IPC: H03K17/61 ,  H03K17/16

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry that includes a pull-up network coupled to a supply voltage and at least one input signal. The IC further includes a first metal oxide semiconductor (MOS) transistor coupled to the pull-up network and to a first bias voltage to reduce a gate-induced drain leakage (GIDL) current of the CMOS circuitry.

公开(公告)号：US20170185094A1

公开(公告)日：2017-06-29

申请号：US14983420

申请日：2015-12-29

Applicant: Silicon Laboratories Inc.

Inventor： Nicholas M. Atkinson ,  Praveen Kallam ,  Timothy T. Rueger

IPC: G05F1/59 ,  G06F1/32 ,  H02J7/00

CPC classification number: G05F1/59 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3243 ,  H02J1/102 ,  H02J7/0052 ,  H02J7/0063 ,  H02J7/34

Abstract: An apparatus includes an integrated circuit (IC). The IC includes a power controller, which includes a regulator and a controller. The regulator receives a plurality of input voltages and provides a regulated output voltage. The controller controls the regulator to generate the regulated output voltage from the plurality of input voltages. The power controller provides power to a load integrated in the IC from a set of arbitrary input voltages. The set of arbitrary input voltages includes the plurality of input voltages.

公开(公告)号：US10355477B2

公开(公告)日：2019-07-16

申请号：US14927810

申请日：2015-10-30

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed Elsayed ,  Matthew Powell ,  Nicholas M. Atkinson ,  Praveen Kallam

IPC: H02J1/10 ,  G06F1/26 ,  H03K19/0185 ,  G06F1/28 ,  G06F1/30 ,  H02J1/00

Abstract: Circuitry and methods are provided that may be implemented to transfer digital signals between multiple voltage domains while some of these domains may be invalid, e.g., such as to transfer a digital signal from a source voltage domain to a destination voltage domain while the voltage of the source domain is zero or invalid. Possible implementations include, but are not limited to, for power selection and distribution in an integrated circuit chip that has multiple power sources (e.g., such as main power supply and a backup power supply), and in which at startup the chip is agnostic of (or is not aware of) which power supply or power supplies is actually powered and available.

公开(公告)号：US09836071B2

公开(公告)日：2017-12-05

申请号：US14983420

申请日：2015-12-29

Applicant: Silicon Laboratories Inc.

Inventor： Nicholas M. Atkinson ,  Praveen Kallam ,  Timothy T. Rueger

IPC: H03L5/00 ,  G05F1/59 ,  H02J7/00 ,  G06F1/32

CPC classification number: G05F1/59 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3243 ,  H02J1/102 ,  H02J7/0052 ,  H02J7/0063 ,  H02J7/34

Abstract: An apparatus includes an integrated circuit (IC). The IC includes a power controller, which includes a regulator and a controller. The regulator receives a plurality of input voltages and provides a regulated output voltage. The controller controls the regulator to generate the regulated output voltage from the plurality of input voltages. The power controller provides power to a load integrated in the IC from a set of arbitrary input voltages. The set of arbitrary input voltages includes the plurality of input voltages.

公开(公告)号：US09964986B2

公开(公告)日：2018-05-08

申请号：US14983413

申请日：2015-12-29

Applicant: Silicon Laboratories Inc.

Inventor： Timothy T. Rueger ,  Praveen Kallam ,  Nicholas M. Atkinson

IPC: G05F3/26

CPC classification number: G05F3/262

Abstract: An apparatus includes an integrated circuit (IC). The IC includes a regulator to receive a plurality of input voltages and to provide a regulated output voltage to a load. The regulator includes a plurality of voltage regulators that receive the plurality of input voltages and provide the regulated output voltage as an output of the regulator. The IC further includes a controller that controls the regulator by using a voltage regulator in the plurality of voltage regulators to generate the regulated output voltage from the plurality of input voltages.

公开(公告)号：US20170185096A1

公开(公告)日：2017-06-29

申请号：US14983413

申请日：2015-12-29

Applicant: Silicon Laboratories Inc.

Inventor： Timothy T. Rueger ,  Praveen Kallam ,  Nicholas M. Atkinson

IPC: G05F3/26

CPC classification number: G05F3/262

Abstract: An apparatus includes an integrated circuit (IC). The IC includes a regulator to receive a plurality of input voltages and to provide a regulated output voltage to a load. The regulator includes a plurality of voltage regulators that receive the plurality of input voltages and provide the regulated output voltage as an output of the regulator. The IC further includes a controller that controls the regulator by using a voltage regulator in the plurality of voltage regulators to generate the regulated output voltage from the plurality of input voltages.

公开(公告)号：US20160105148A1

公开(公告)日：2016-04-14

申请号：US14509754

申请日：2014-10-08

Applicant: Silicon Laboratories Inc.

Inventor： Matthew R. Powell ,  Axel Thomsen ,  Nicholas M. Atkinson

IPC: H03B5/24

CPC classification number: H03B5/24 ,  H03K3/011 ,  H03K3/0231

Abstract: A method includes using a current source to provide a charging current to a capacitor of a resistor-capacitor (RC) tank of an RC oscillator. The method includes using a resistor of the current source as a resistor for the RC tank.

Abstract translation: 一种方法包括使用电流源向RC振荡器的电阻 - 电容（RC）槽的电容器提供充电电流。 该方法包括使用电流源的电阻器作为RC箱的电阻器。

公开(公告)号：US20190123734A1

公开(公告)日：2019-04-25

申请号：US16221552

申请日：2018-12-16

Applicant: Silicon Laboratories Inc.

Inventor： Arnab Kumar Dutta ,  Essam Atalla ,  Nicholas M. Atkinson

IPC: H03K17/16

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry that includes a pull-up network coupled to a supply voltage and at least one input signal. The IC further includes a first metal oxide semiconductor (MOS) transistor coupled to the pull-up network and to a first bias voltage to reduce a gate-induced drain leakage (GIDL) current of the CMOS circuitry.

公开(公告)号：US20180234089A1

公开(公告)日：2018-08-16

申请号：US15429690

申请日：2017-02-10

Applicant: Silicon Laboratories Inc.

Inventor： Arnab Kumar Dutta ,  Essam Atalla ,  Nicholas M. Atkinson

IPC: H03K17/16

CPC classification number: H03K17/161 ,  H03K2217/0036

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry that includes a pull-up network coupled to a supply voltage and at least one input signal. The IC further includes a first metal oxide semiconductor (MOS) transistor coupled to the pull-up network and to a first bias voltage to reduce a gate-induced drain leakage (GIDL) current of the CMOS circuitry.

公开(公告)号：US20170126005A1

公开(公告)日：2017-05-04

申请号：US14927810

申请日：2015-10-30

Applicant: Silicon Laboratories Inc.

Inventor： Mohamed Elsayed ,  Matthew Powell ,  Nicholas M. Atkinson ,  Praveen Kallam

IPC: H02J1/10 ,  H03K17/687

CPC classification number: H02J1/10 ,  G06F1/26 ,  G06F1/28 ,  G06F1/305 ,  H02J2001/008 ,  H03K19/0185

Abstract: Circuitry and methods are provided that may be implemented to transfer digital signals between multiple voltage domains while some of these domains may be invalid, e.g., such as to transfer a digital signal from a source voltage domain to a destination voltage domain while the voltage of the source domain is zero or invalid. Possible implementations include, but are not limited to, for power selection and distribution in an integrated circuit chip that has multiple power sources (e.g., such as main power supply and a backup power supply), and in which at startup the chip is agnostic of (or is not aware of) which power supply or power supplies is actually powered and available.