公开(公告)号：US11262786B1

公开(公告)日：2022-03-01

申请号：US17123949

申请日：2020-12-16

Applicant: Silicon Laboratories Inc.

Inventor： Hegong Wei ,  Brian Brunn ,  Paul Zavalney

IPC: G06F1/12 ,  G06F1/10 ,  H03K5/135

Abstract: A circuit for compensating for data delay is disclosed. The circuit utilizes an internal clock signal. This internal clock signal passes through an I/O buffer to become an external clock. This external clock is then passed through the I/O buffer to create the return clock signal. This difference between the internal clock signal and the return clock signal is defined as I/O delay. In certain embodiments, this I/O delay may be more than one clock period, which typically causes incorrect operation of synchronous logic. The present circuit allows for a I/O delay of N clock periods, wherein N is greater than one, through a novel approach to capturing and synchronizing the return data. This allows high speed microcontrollers to utilize lower speed I/O buffers to reduce interference, or allows these microcontrollers to interface with slower external devices.