公开(公告)号：US20200373930A1

公开(公告)日：2020-11-26

申请号：US16417700

申请日：2019-05-21

Applicant: Silicon Laboratories Inc.

Inventor： Mudit Srivastava ,  Paul Zavalney ,  William Durbin

IPC: H03M1/00

Abstract: In one embodiment, an apparatus includes: a digital-to-analog converter (DAC) circuit having a digital portion to receive a digital value and an analog portion to generate an analog voltage based on the digital value; and a refresh circuit coupled to the DAC circuit to clock gate provision of a first clock signal to the DAC circuit when the digital portion is inactive.

公开(公告)号：US10848165B1

公开(公告)日：2020-11-24

申请号：US16417700

申请日：2019-05-21

Applicant: Silicon Laboratories Inc.

Inventor： Mudit Srivastava ,  Paul Zavalney ,  William Durbin

IPC: H03M1/66 ,  H03M1/00

Abstract: In one embodiment, an apparatus includes: a digital-to-analog converter (DAC) circuit having a digital portion to receive a digital value and an analog portion to generate an analog voltage based on the digital value; and a refresh circuit coupled to the DAC circuit to clock gate provision of a first clock signal to the DAC circuit when the digital portion is inactive.

公开(公告)号：US10180839B2

公开(公告)日：2019-01-15

申请号：US15061018

申请日：2016-03-04

Applicant: Silicon Laboratories Inc.

Inventor： Mark W. Johnson ,  Paul Zavalney ,  Marius Grannæs ,  Oeivind A. G. Loe

IPC: G06F9/40 ,  G06F12/12 ,  G06F9/30 ,  G06F9/32 ,  G06F12/0875 ,  G06F9/38 ,  G06F12/121

Abstract: An apparatus includes a processor and a loop cache coupled to the processor. The loop cache provides to the processor instructions corresponding to a loop in the instructions. The loop cache includes a persistence counter.

公开(公告)号：US09106176B2

公开(公告)日：2015-08-11

申请号：US13731081

申请日：2012-12-30

Applicant: Silicon Laboratories Inc.

Inventor： Kenneth A Berringer ,  Axel Thomsen ,  Pedro Pachuca ,  Brent Wilson ,  Jinwen Xiao ,  Scott Willingham ,  Kenneth W Fernald ,  Paul Zavalney

IPC: H02P6/00 ,  H02P21/06 ,  H02P7/00

CPC classification number: H02P21/06 ,  H02P31/00

Abstract: A motor control apparatus to control a motor external to the motor control apparatus includes a microcontroller unit (MCU). The MCU includes mixed signal motor control circuitry adapted to perform back electromotive force (EMF) motor control in a first mode of operation. The mixed signal motor control circuitry is further adapted to perform field oriented control (FOC) in a second mode of operation.

Abstract translation: 用于控制电动机控制装置外部的电动机的电动机控制装置包括微控制器单元（MCU）。 MCU包括混合信号电动机控制电路，其适于在第一操作模式下执行反电动势（EMF）电动机控制。 混合信号电机控制电路还适于在第二操作模式中执行场定向控制（FOC）。

公开(公告)号：US20140184116A1

公开(公告)日：2014-07-03

申请号：US13731081

申请日：2012-12-30

Applicant: SILICON LABORATORIES INC.

Inventor： Kenneth A. Berringer ,  Axel Thomsen ,  Pedro Pachuca ,  Brent Wilson ,  Jinwen Xiao ,  Scott Willingham ,  Kenneth W. Fernald ,  Paul Zavalney

IPC: H02P6/18 ,  H02P25/02

CPC classification number: H02P21/06 ,  H02P31/00

Abstract: A motor control apparatus to control a motor external to the motor control apparatus includes a microcontroller unit (MCU). The MCU includes mixed signal motor control circuitry adapted to perform back electromotive force (EMF) motor control in a first mode of operation. The mixed signal motor control circuitry is further adapted to perform field oriented control (FOC) in a second mode of operation.

Abstract translation: 用于控制电动机控制装置外部的电动机的电动机控制装置包括微控制器单元（MCU）。 MCU包括混合信号电动机控制电路，其适于在第一操作模式下执行反电动势（EMF）电动机控制。 混合信号电动机控制电路还适于在第二操作模式中执行场定向控制（FOC）。

公开(公告)号：US11374600B1

公开(公告)日：2022-06-28

申请号：US17160835

申请日：2021-01-28

Applicant: Silicon Laboratories Inc.

Inventor： Thomas Saroshan David ,  Michael Johnson ,  Paul Zavalney

IPC: H04B1/10 ,  G06F1/10 ,  G06F13/20 ,  G06F13/42 ,  H03L7/081

Abstract: In one example, an apparatus includes: a radio frequency (RF) receiver to receive an RF signal; a media access control (MAC) circuit to receive data and output MAC-processed data according to a clock signal that is phase delayed with respect to a source clock signal when the RF receiver is active; and an interference mitigation circuit to receive the MAC-processed data and provide the MAC-processed data to a physical circuit resynchronized to the source clock signal.

公开(公告)号：US11262786B1

公开(公告)日：2022-03-01

申请号：US17123949

申请日：2020-12-16

Applicant: Silicon Laboratories Inc.

Inventor： Hegong Wei ,  Brian Brunn ,  Paul Zavalney

IPC: G06F1/12 ,  G06F1/10 ,  H03K5/135

Abstract: A circuit for compensating for data delay is disclosed. The circuit utilizes an internal clock signal. This internal clock signal passes through an I/O buffer to become an external clock. This external clock is then passed through the I/O buffer to create the return clock signal. This difference between the internal clock signal and the return clock signal is defined as I/O delay. In certain embodiments, this I/O delay may be more than one clock period, which typically causes incorrect operation of synchronous logic. The present circuit allows for a I/O delay of N clock periods, wherein N is greater than one, through a novel approach to capturing and synchronizing the return data. This allows high speed microcontrollers to utilize lower speed I/O buffers to reduce interference, or allows these microcontrollers to interface with slower external devices.

公开(公告)号：US20170255467A1

公开(公告)日：2017-09-07

申请号：US15061018

申请日：2016-03-04

Applicant: Silicon Laboratories Inc.

Inventor： Mark W. Johnson ,  Paul Zavalney ,  Marius Grannæs ,  Oeivind A. G. Loe

IPC: G06F9/30

CPC classification number: G06F9/30047 ,  G06F9/30065 ,  G06F9/325 ,  G06F9/3806 ,  G06F9/381 ,  G06F12/0875 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/452 ,  Y02D10/13

Abstract: An apparatus includes a processor and a loop cache coupled to the processor. The loop cache provides to the processor instructions corresponding to a loop in the instructions. The loop cache includes a persistence counter.