公开(公告)号：US11711084B2

公开(公告)日：2023-07-25

申请号：US17714081

申请日：2022-04-05

Applicant: Space Exploration Technologies Corp. ,  Iliana Ghazali

Inventor： David Francois Jacquet ,  Mostafa Ghazali ,  Masoud Kahrizi ,  Andras Tantos

IPC: H03L7/07 ,  H03L7/197

CPC classification number: H03L7/07 ,  H03L7/1976

Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal. The IC chips is configured to a reference time signal based on the timing signal and the reference clock signal. The IC chip includes a phase lock loop (PLL). The PLL is synchronized based on the reference time signal.

公开(公告)号：US20220231691A1

公开(公告)日：2022-07-21

申请号：US17714081

申请日：2022-04-05

Applicant: Space Exploration Technologies Corp.

Inventor： David Francois Jacquet ,  Mostafa Ghazali ,  Masoud Kahrizi ,  Andras Tantos

IPC: H03L7/07 ,  H03L7/197

Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal. The IC chips is configured to a reference time signal based on the timing signal and the reference clock signal. The IC chip includes a phase lock loop (PLL). The PLL is synchronized based on the reference time signal.

公开(公告)号：US11133806B1

公开(公告)日：2021-09-28

申请号：US16858675

申请日：2020-04-26

Applicant: Space Exploration Technologies Corp.

Inventor： David Francois Jacquet ,  Mostafa Ghazali ,  Masoud Kahrizi ,  Andras Tantos

IPC: H03L7/07 ,  H03L7/197

Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; a second IC chip configured to receive the timing signal from the first IC chip and the reference clock signal; and a third IC chip configured to receive the timing signal from the second IC chip and the reference clock signal. The second IC chip is electrically coupled between the first and third IC chips. The first, second, and third IC chips include respectively first, second, and third phase lock loop (PLL). The first, second, and third IC chips are configured to generate respective first, second, and third reference time signals based on the timing signal and the reference clock signal. The first, second, and third PLLs are synchronized to each other based on the respective first, second, and third reference time signals.

公开(公告)号：US12191865B2

公开(公告)日：2025-01-07

申请号：US18225477

申请日：2023-07-24

Applicant: Space Exploration Technologies Corp. ,  Iliana Ghazali

Inventor： David Francois Jacquet ,  Mostafa Ghazali ,  Masoud Kahrizi ,  Andras Tantos

IPC: H03L7/07 ,  H03L7/197

Abstract: In an embodiment, an apparatus includes one or more timing components configured to generate a reference time signal based on a timing signal and a reference clock signal. The apparatus includes phase lock loop (PLL) configured to generate a synchronized output clock signal based on the reference clock signal and the reference time signal.

公开(公告)号：US11329653B2

公开(公告)日：2022-05-10

申请号：US17401208

申请日：2021-08-12

Applicant: Space Exploration Technologies Corp.

Inventor： David Francois Jacquet ,  Mostafa Ghazali ,  Masoud Kahrizi ,  Andras Tantos

IPC: H03L7/07 ,  H03L7/197

Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; and a second IC chip configured to receive the timing signal and the reference clock signal. The first and second IC chips are configured to generate respective first and second reference time signals based on the timing signal and the reference clock signal. The first and second IC chips include a respective first phase lock loop (PLL) and second PLL. The first PLL and the second PLL are synchronized to each other based on the first reference time signal and the second reference time signal.

公开(公告)号：US20230378960A1

公开(公告)日：2023-11-23

申请号：US18225477

申请日：2023-07-24

Applicant: Space Exploration Technologies Corp.

Inventor： David Francois Jacquet ,  Mostafa Ghazali ,  Masoud Kahrizi ,  Andras Tantos

IPC: H03L7/07 ,  H03L7/197

CPC classification number: H03L7/07 ,  H03L7/1976

Abstract: In an embodiment, an apparatus includes one or more timing components configured to generate a reference time signal based on a timing signal and a reference clock signal. The apparatus includes phase lock loop (PLL) configured to generate a synchronized output clock signal based on the reference clock signal and the reference time signal.

公开(公告)号：US20210376837A1

公开(公告)日：2021-12-02

申请号：US17401208

申请日：2021-08-12

Applicant: Space Exploration Technologies Corp.

Inventor： David Francois Jacquet ,  Mostafa Ghazali ,  Masoud Kahrizi ,  Andras Tantos

IPC: H03L7/07 ,  H03L7/197

Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; and a second IC chip configured to receive the timing signal and the reference clock signal. The first and second IC chips are configured to generate respective first and second reference time signals based on the timing signal and the reference clock signal. The first and second IC chips include a respective first phase lock loop (PLL) and second PLL. The first PLL and the second PLL are synchronized to each other based on the first reference time signal and the second reference time signal.