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1.发明授权公开(公告)号：US11967965B2
公开(公告)日：2024-04-23
申请号：US17806735
申请日：2022-06-14
发明人： Raja Prabhu J , Ankit Seedher , Srinath Sridharan , Rakesh Kumar Gupta , Nitesh Naidu , Shivam Agrawal , Jeevabharathi G , Purva Choudhary
CPC分类号： H03L7/199 , H03L7/0818 , H03L7/1976 , H03L7/24
摘要： Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.
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2.发明授权公开(公告)号：US11955979B2
公开(公告)日：2024-04-09
申请号：US17835292
申请日：2022-06-08
申请人： Apple Inc.
发明人： Reetika K Agarwal , Abbas Komijani , Hongrui Wang
CPC分类号： H03L7/0891 , H03C3/0941 , H03L7/091 , H03L7/099 , H03L7/185 , H03L7/1976 , H04L7/033
摘要： An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.
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公开(公告)号：US11909408B2
公开(公告)日：2024-02-20
申请号：US17907099
申请日：2021-03-24
发明人： Shengwen Xiang , Ying Liu
CPC分类号： H03L7/1974 , G06F1/10
摘要： A SerDes module clock network architecture comprises, a reference clock input port, a plurality of data transmission channels, several user logic interfaces, several frequency division branches and a phase locked loop. The reference lock input port receives an input clock and conveys the input clock to the phase locked loop, the phase locked loop receives the input lock and outputs a PLL output clock signal, the PLL output clock signal is conveyed to the plurality of data transmission channels, and the PLL output clock signal is conveyed to the frequency division branches, and after frequency division, user interface clocks are output and conveyed to the user logic interfaces. When the PLL output clock signal in a SerDes is provided to an internal dedicated channel, several frequency division branches are also divided, and after frequency division, the signal is output to the user logic interfaces for use by an FPGA.
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公开(公告)号：US20240007116A1
公开(公告)日：2024-01-04
申请号：US17853323
申请日：2022-06-29
申请人： ATI Technologies ULC
发明人： Erwin Chi Wang Pang
CPC分类号： H03L7/1974 , H03L7/0816 , H03L7/0805
摘要： An apparatus and method for efficiently generating clock signals. An integrated circuit includes multiple clock dividers both at its I/O boundaries and across its semiconductor die. A clock divider receives an input clock signal, and an indication of a reduction factor that is a positive, non-zero and a non-integer value less than one. The clock divider generates an output clock signal based on the input clock signal and the reduction factor. The reduction factor can be an M-bit pattern where M is a positive, non-zero integer greater than one. Therefore, the clock divider generates the output clock signal with a reduced clock rate that has a smallest configurable granularity that is 1/M of the input clock frequency. An asserted bit in the M-bit pattern indicates that the output clock signal should have an asserted value during a corresponding clock cycle of the input clock signal.
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公开(公告)号：US20230412177A1
公开(公告)日：2023-12-21
申请号：US17918099
申请日：2021-03-03
发明人： Jinbo LI
CPC分类号： H03L7/1978 , H03L7/1803 , H03K19/20 , H03K5/131
摘要： Disclosed is a pulse elimination circuit, a voltage detection circuit and a detection method, referring to a field of electronic circuit technology. The pulse elimination circuit comprises: a clock generation circuit configured to receive a logic signal and a first input signal and generate a clock signal according to the logic signal and the first input signal; a counter coupled with the clock generation circuit and configured to receive the clock signal and count a number of cycles of the clock signal to generate a second input signal; a signal output circuit coupled to the counter and configured to supply a first input signal to the clock generation circuit and generate a pulse elimination signal based on the second input signal. Therefore, in a process of voltage detection, this circuit can eliminate a false trigger caused by short pulse and improve voltage detection accuracy.
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公开(公告)号：US20230387924A1
公开(公告)日：2023-11-30
申请号：US18307475
申请日：2023-04-26
发明人： Yusuke IMANAKA , Atsushi MOTOZAWA
CPC分类号： H03L7/0998 , H03L7/1974
摘要： A semiconductor device includes a phase interpolation circuit including an N-bit current digital-analog conversion circuit, a switch circuit, a capacitive element, an inverter, and a control logic circuit. The control logic circuit detects an end of a phase interpolation operation by using an output result of the inverter and outputs a first control signal for turning off the current digital-analog conversion circuit. Also, the control logic circuit detects the end of the phase interpolation operation by using the output result of the inverter and outputs a second control signal for turning off the inverter.
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公开(公告)号：US20230378960A1
公开(公告)日：2023-11-23
申请号：US18225477
申请日：2023-07-24
CPC分类号： H03L7/07 , H03L7/1976
摘要： In an embodiment, an apparatus includes one or more timing components configured to generate a reference time signal based on a timing signal and a reference clock signal. The apparatus includes phase lock loop (PLL) configured to generate a synchronized output clock signal based on the reference clock signal and the reference time signal.
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公开(公告)号：US11817825B2
公开(公告)日：2023-11-14
申请号：US17894505
申请日：2022-08-24
发明人： Kensaku Isohata
CPC分类号： H03B5/32 , H03B5/04 , H03L7/099 , H03L7/1974 , H03B2200/0018 , H03B2200/0088
摘要： An oscillator includes a first resonator element, a circuit element configured to oscillate the first resonator element to generate an oscillation signal, a first package which includes a substrate, and has a housing space configured to house the first resonator element and the circuit element at one principal surface side of the substrate, a second resonator element which is disposed at another principal surface side of the substrate, and an oscillation frequency of which is controlled based on the oscillation signal, and a leg part which is disposed at the another principal surface side of the substrate, and which is arranged so as to surround the second resonator element in a plan view of the substrate.
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公开(公告)号：US11784651B2
公开(公告)日：2023-10-10
申请号：US17512231
申请日：2021-10-27
申请人： NXP B.V.
CPC分类号： H03L7/0992 , H03L7/0814 , H03L7/0995 , H03L7/1974 , H03M3/30
摘要： An oscillator provides a plurality of clock signals, including a first clock signal having a first frequency and a first period, wherein each clock signal has the first frequency and is phase shifted from the first clock signal by an integer times a predetermined fractional amount of the first period. A multiphase frequency divider receives the plurality of clock signals and provides a divided clock output, and includes an integer frequency divider which provides the divided clock output based on a modified clock input and a clock selector which provides a current clock as the modified clock input during a first portion of the divided clock output and a next clock as the modified clock input during a subsequent portion of the divided clock output. The next clock is selected from the plurality of clock signals based on a selected fractional phase shift amount indicated by a sigma-delta modulator.
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10.发明授权公开(公告)号：US11777510B2
公开(公告)日：2023-10-03
申请号：US17964377
申请日：2022-10-12
发明人： Baekmin Lim , Seungjin Kim , Seunghyun Oh
CPC分类号： H03L7/1976 , H03L7/081 , H03L7/093
摘要： A fractional divider processing circuitry is to receive one of a plurality of clock signals as an input clock signal, and generate a first division clock signal based on the input clock signal and a first control signal. Phases of the plurality of clock signals partially overlap each other. The processing circuitry generates a delta-sigma modulation signal based on the first division clock signal and a frequency control word, and generates a second division clock signal based on the plurality of clock signals, the first division clock signal and a second control signal. The second control signal corresponds to a quantization noise of the delta-sigma modulation signal. The processing circuitry generates the second control signal and a digital control word based on the quantization noise of the delta-sigma modulator. The processing circuitry generates a final division clock signal based on the second division clock signal and the digital control word.
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