Device for reducing bipolar effects in mos integrated circuits
    1.
    发明授权
    Device for reducing bipolar effects in mos integrated circuits 失效
    MOS集成电路中减少双极效应的器件

    公开(公告)号:US3573509A

    公开(公告)日:1971-04-06

    申请号:US3573509D

    申请日:1968-09-09

    CPC classification number: H01L27/088 G11C19/184 H01L27/108 H01L29/0638

    Abstract: A capacitive pullup, two-phase shift register formed by Pchannel enhancement mode MOS transistors is disclosed as the embodiment of the invention. As a result of the capacitive coupling, a P-type diffusion which is normally negative will go positive in some instances. This forward biases the normally reverse biased PN junction between the P-type diffusion and the N-type substrate, injecting carriers into the substrate which may be collected at any other negatively biased P-type diffusion which then functions as the collector of a bipolar transistor. This collector current may result in the loss of stored logic information. To minimize these effects, a P-type collector diffusion is disposed adjacent to each potential emitting diffusion to collect the spurious carriers injected into the substrate before they cause the loss of stored data.

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