公开(公告)号：US20200012304A1

公开(公告)日：2020-01-09

申请号：US16208159

申请日：2018-12-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aalok Dyuti SAHA ,  Bhaskar RAMACHANDRAN ,  Dattatreya BARAGUR SURYANARAYANA

IPC: G05F1/573 ,  G05F1/567 ,  G05D23/20 ,  G01R19/165

Abstract: An apparatus includes a power transistor to conduct a load current from a supply voltage node to an output node and a current sense circuit coupled to the power transistor. The current sense circuit generates a current sense current proportional to the load current. A temperature sense circuit is included to generate a temperature sense voltage proportional to the temperature of the power FET. A thermal limit circuit is coupled to the temperature sense circuit. A current limit circuit is coupled to the current sense circuit and to the thermal limit circuit. The current limit circuit generates a control signal on a current limit circuit output node. The control signal is responsive to the current sense current and to a first current from the thermal limit circuit. The current limit circuit output node is coupled to a control input of the power transistor.

公开(公告)号：US20230008179A1

公开(公告)日：2023-01-12

申请号：US17858222

申请日：2022-07-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aalok Dyuti SAHA

IPC: H02M1/00 ,  H02M3/158

Abstract: In an example, a system includes a differential amplifier having a first input terminal and a second input terminal, the differential amplifier configured to be coupled to a boost diode of a boost converter. The system also includes an input diode coupled to the first input terminal and the second input terminal. The system includes a pull-up circuit coupled to the input diode and configured to be coupled to the boost diode. The system also includes a pull-down circuit coupled to the pull-up circuit. The system includes a transistor coupled to the pull-up circuit and the pull-down circuit.

公开(公告)号：US20200014347A1

公开(公告)日：2020-01-09

申请号：US16185591

申请日：2018-11-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aalok Dyuti SAHA ,  Bhaskar RAMACHANDRAN

IPC: H03F3/45

Abstract: A servo-amplifier includes a first bipolar transistor, a second bipolar transistor, a cascode transistor, and a bias transistor. The second bipolar transistor includes an emitter terminal that is connected to an emitter terminal of the first bipolar transistor to form a differential amplifier. The cascode transistor includes a source terminal that is connected to a collector terminal of the first bipolar transistor. The bias transistor is coupled to the first bipolar transistor, the second bipolar transistor and the cascode transistor. The bias transistor is configured to generate a bias voltage to drive a gate terminal of the cascode transistor based on a voltage at a base terminal of the first bipolar transistor and a voltage at a base terminal of the second bipolar transistor. As a result, neither of the bipolar transistors enters a saturation region during transient or steady state operation.

公开(公告)号：US20200011906A1

公开(公告)日：2020-01-09

申请号：US16230564

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bhaskar RAMACHANDRAN ,  Kushal D. MURTHY ,  Aalok Dyuti SAHA

IPC: G01R19/165 ,  G01R19/155

Abstract: A device includes a first transistor coupled to an input voltage source and to an output voltage node and an amplifier comprising a first input, a second input, and an output. The device also includes a second transistor coupled to the input voltage source and the first input of the amplifier and a third transistor coupled to the second transistor and a ground node. The third transistor includes a control terminal coupled to the output of the amplifier. The device also includes a first voltage-controlled voltage source coupled to a control terminal of the first transistor and a control terminal of the second transistor and a second voltage-controlled voltage source coupled to the first transistor and the second input of the amplifier.

公开(公告)号：US20240283350A9

公开(公告)日：2024-08-22

申请号：US17891456

申请日：2022-08-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vasishta KIDAMBI ,  Harsh PATEL ,  Aalok Dyuti SAHA ,  Subrato ROY

IPC: H02M1/08

CPC classification number: H02M1/08

Abstract: One example includes a testing method that includes connecting a capacitor having a first capacitance to an output terminal of an integrated circuit (IC). The method can also include generating pulse signal responsive to an enable signal provided at at least one input terminal of the IC and providing a drive signal to the output terminal to cause a linearly increasing voltage across the capacitor responsive to the pulse signal. The method can also include measuring a no-load delay. The method can also include measuring the linearly increasing voltage at the output terminal responsive to the drive signal. The method can also include determining a first capacitance charge time for the capacitor responsive to the linearly increasing voltage reaching a threshold and determining a second capacitance charge delay for a second capacitance based on the first capacitance charge time and the no-load delay.

公开(公告)号：US20230072953A1

公开(公告)日：2023-03-09

申请号：US17891456

申请日：2022-08-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vasishta KIDAMBI ,  Harsh PATEL ,  Aalok Dyuti SAHA ,  Subrato ROY

IPC: H02M1/08

Abstract: One example includes a testing method that includes connecting a capacitor having a first capacitance to an output terminal of an integrated circuit (IC). The method can also include generating pulse signal responsive to an enable signal provided at at least one input terminal of the IC and providing a drive signal to the output terminal to cause a linearly increasing voltage across the capacitor responsive to the pulse signal. The method can also include measuring a no-load delay. The method can also include measuring the linearly increasing voltage at the output terminal responsive to the drive signal. The method can also include determining a first capacitance charge time for the capacitor responsive to the linearly increasing voltage reaching a threshold and determining a second capacitance charge delay for a second capacitance based on the first capacitance charge time and the no-load delay.