公开(公告)号：US20190204361A1

公开(公告)日：2019-07-04

申请号：US15859470

申请日：2017-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Tikno HARJONO ,  Vijay KRISHNAMURTHY ,  Min CHU ,  Kuntal JOARDAR ,  Gary Eugene DAUM ,  Subrato ROY ,  Vinayak HEGDE ,  Ankur CHAUHAN ,  Sathish VALLAMKONDA ,  Md Abidur RAHMAN ,  Eung Jung KIM

IPC: G01R15/14 ,  H01L27/06 ,  H01L49/02 ,  H01L25/18 ,  H03K17/567

CPC classification number: G01R15/146 ,  H01L25/18 ,  H01L27/0629 ,  H01L28/20 ,  H03K17/567

Abstract: An electronic device comprises: a first semiconductor die; a power transistor integrated in the first semiconductor die, the power transistor comprising a gate, a first terminal, and a second terminal; a sense transistor integrated in the first semiconductor die, the sense transistor comprising a gate coupled to the gate of the power transistor, a first terminal, and a second terminal coupled to the second terminal of the power transistor; and a first resistor integrated in the first semiconductor die, the first resistor comprising a polysilicon section and a metal section coupled to the polysilicon section, the first resistor comprising a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the first terminal of the sense transistor.

公开(公告)号：US20180262184A1

公开(公告)日：2018-09-13

申请号：US15857135

申请日：2017-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ankur CHAUHAN ,  Subrato ROY

IPC: H03K5/08

CPC classification number: H03K5/086 ,  G05F1/46 ,  G05F1/573

Abstract: An example current limiting apparatus comprises a first transistor to carry a first current; a sense transistor coupled to the first transistor, the sense transistor to carry a sense current that is a function of the first current; a first amplifier coupled to the first transistor and the sense transistor, the amplifier to achieve a common voltage potential on terminals of the first and the sense transistors; a second amplifier coupled to the first amplifier and the sense transistor, the second amplifier to control the first and sense transistors based on the sense current; and a circuit coupled to the first and second amplifiers, the circuit to control an input to the second amplifier based on an input to the first amplifier such that a current limit of the first transistor remains below a programmed current limit of the first transistor.

公开(公告)号：US20240283350A9

公开(公告)日：2024-08-22

申请号：US17891456

申请日：2022-08-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vasishta KIDAMBI ,  Harsh PATEL ,  Aalok Dyuti SAHA ,  Subrato ROY

IPC: H02M1/08

CPC classification number: H02M1/08

Abstract: One example includes a testing method that includes connecting a capacitor having a first capacitance to an output terminal of an integrated circuit (IC). The method can also include generating pulse signal responsive to an enable signal provided at at least one input terminal of the IC and providing a drive signal to the output terminal to cause a linearly increasing voltage across the capacitor responsive to the pulse signal. The method can also include measuring a no-load delay. The method can also include measuring the linearly increasing voltage at the output terminal responsive to the drive signal. The method can also include determining a first capacitance charge time for the capacitor responsive to the linearly increasing voltage reaching a threshold and determining a second capacitance charge delay for a second capacitance based on the first capacitance charge time and the no-load delay.

公开(公告)号：US20230072953A1

公开(公告)日：2023-03-09

申请号：US17891456

申请日：2022-08-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vasishta KIDAMBI ,  Harsh PATEL ,  Aalok Dyuti SAHA ,  Subrato ROY

IPC: H02M1/08

Abstract: One example includes a testing method that includes connecting a capacitor having a first capacitance to an output terminal of an integrated circuit (IC). The method can also include generating pulse signal responsive to an enable signal provided at at least one input terminal of the IC and providing a drive signal to the output terminal to cause a linearly increasing voltage across the capacitor responsive to the pulse signal. The method can also include measuring a no-load delay. The method can also include measuring the linearly increasing voltage at the output terminal responsive to the drive signal. The method can also include determining a first capacitance charge time for the capacitor responsive to the linearly increasing voltage reaching a threshold and determining a second capacitance charge delay for a second capacitance based on the first capacitance charge time and the no-load delay.