公开(公告)号：US20210409248A1

公开(公告)日：2021-12-30

申请号：US17083008

申请日：2020-10-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek MANIAN ,  Amit RANE ,  Ashwin Kottilvalappil VIJAYAN

IPC: H04L27/01 ,  H04L25/03

Abstract: A linear retimer includes an equalizer, a clock recovery circuit, a sample and hold (S/H) circuit, and a linear driver. The equalizer receives an input signal and outputs an equalized signal. The clock recovery circuit receives the equalized signal and outputs a clock signal. The S/H circuit receives the equalized signal and the clock signal and outputs a retimed signal. The linear driver receives the retimed signal and outputs a recovered signal. The S/H circuit is configured to preserve a voltage of the equalized signal in the retimed signal. In some examples, the S/H circuit is part of a linear three-tap feedforward equalizer, and the linear driver receives an output of the feedforward equalizer. The linear retimer can be placed between a transmitter and a channel or after the channel.

公开(公告)号：US20210409246A1

公开(公告)日：2021-12-30

申请号：US17095869

申请日：2020-11-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek MANIAN ,  Ashwin Kottilvalappil VIJAYAN ,  Amit RANE ,  Ashkan ROSHAN ZAMIR

IPC: H04L25/03 ,  G11C27/02 ,  H03H17/06 ,  H03F3/45 ,  H03H11/04 ,  H03F3/183 ,  G05F1/56

Abstract: An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N−1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.

公开(公告)号：US20210159896A1

公开(公告)日：2021-05-27

申请号：US17163894

申请日：2021-02-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Huanzhang HUANG ,  Amit RANE

IPC: H03K17/00 ,  G06F13/38 ,  H03K19/003 ,  H03K17/56

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

公开(公告)号：US20210075650A1

公开(公告)日：2021-03-11

申请号：US16778955

申请日：2020-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amit RANE ,  Charles Michael CAMPBELL ,  Suzanne Mary VINING

IPC: H04L25/03 ,  H04L7/00

Abstract: At least some aspects of the present disclosure provide for a method. In at least one examples, the method includes applying first equalization to a received data signal to generate an equalizer signal and comparing the equalized signal to each of a plurality of reference voltages for a predetermined period of time per respective reference voltage to generate a comparison result. The method further includes determining a plurality of counts with each count of the plurality of counts uniquely corresponding to a number of rising edges in the comparison result for each of the plurality of reference voltages. The method further includes comparing at least one of the plurality of counts to at least another of the plurality of counts to determine a relationship among the plurality of counts and applying second equalization to the received data signal based on the determined relationship among the plurality of counts.

公开(公告)号：US20200084069A1

公开(公告)日：2020-03-12

申请号：US16128605

申请日：2018-09-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amit RANE

IPC: H04L25/03

Abstract: An apparatus includes a clockless decision feedback equalization (DFE) loop. The clockless DFE loop includes a summation circuit configured to combine a multi-level input signal and a multi-level feedback signal. The clockless DFE loop also includes a multi-bit quantizer configured to provide the multi-level feedback signal based on an output of the summation circuit. The clockless DFE loop also includes one or more analog delay circuits configured to delay the multi-level feedback signal to the summation circuit. The clockless DFE loop also includes a DFE tap circuit configured to apply signed DFE tap weights to the multi-level feedback signal.

公开(公告)号：US20200044686A1

公开(公告)日：2020-02-06

申请号：US16599377

申请日：2019-10-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek MANIAN ,  Amit RANE

IPC: H04B1/58 ,  H03K19/0175 ,  H04L25/02

Abstract: A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.

公开(公告)号：US20200350899A1

公开(公告)日：2020-11-05

申请号：US16936462

申请日：2020-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Huanzhang HUANG ,  Amit RANE

IPC: H03K17/00 ,  G06F13/38 ,  H03K19/003 ,  H03K17/56

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

公开(公告)号：US20200052684A1

公开(公告)日：2020-02-13

申请号：US16535557

申请日：2019-08-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Huanzhang HUANG ,  Amit RANE

IPC: H03K17/00 ,  G06F13/38 ,  H03K17/56 ,  H03K19/003

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

公开(公告)号：US20190280729A1

公开(公告)日：2019-09-12

申请号：US16118621

申请日：2018-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek MANIAN ,  Amit RANE

IPC: H04B1/58 ,  H03K19/0175 ,  H04L25/02

Abstract: A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.

公开(公告)号：US20180191321A1

公开(公告)日：2018-07-05

申请号：US15394931

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amit RANE ,  Dongwei CHEN

IPC: H03G1/00 ,  H03F3/45 ,  H03G3/30

CPC classification number: H03G1/007 ,  H03F1/3211 ,  H03F3/45071 ,  H03F3/45098 ,  H03F3/45479 ,  H03F2203/45488 ,  H03G3/3089 ,  H03G2201/708

Abstract: An equalizer, in at least some embodiments, comprises an amplifier configured to produce an amplified voltage signal that is a function of an ambient temperature affecting the equalizer. The equalizer also includes a linear equalizer stage coupled to the amplifier and comprising a transistor having a resistance controlled by the amplified voltage signal. The linear equalizer stage is configured to produce a voltage output signal having a gain that is dependent on the transistor resistance and on a frequency of the amplified voltage signal.