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公开(公告)号：US20240137198A1
公开(公告)日：2024-04-25
申请号：US18309587
申请日：2023-04-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abishek MANIAN , Ashkan ROSHAN ZAMIR , Yonghui TANG , Robin GUPTA , Michael G. VRAZEL
CPC classification number: H04L7/0016 , H04L25/03012
Abstract: A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.
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公开(公告)号：US20190280729A1
公开(公告)日：2019-09-12
申请号：US16118621
申请日：2018-08-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abishek MANIAN , Amit RANE
IPC: H04B1/58 , H03K19/0175 , H04L25/02
Abstract: A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.
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公开(公告)号：US20200228303A1
公开(公告)日：2020-07-16
申请号：US16831867
申请日：2020-03-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abishek MANIAN , Michael Gerald VRAZEL
Abstract: A circuit includes a phase and frequency detector circuit to generate a first phase detect signal indicative of whether a polarity of a first clock is the same as a polarity of a second clock upon occurrence of an edge of a data signal. The second clock being 90 degrees out of phase with respect to the first clock. A lock detect circuit determines, based on the first phase detect signal, that a third clock is one of frequency and phase locked to the data signal, frequency and quadrature locked to the data signal, and not frequency locked to the data signal.
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公开(公告)号：US20200044686A1
公开(公告)日：2020-02-06
申请号：US16599377
申请日：2019-10-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abishek MANIAN , Amit RANE
IPC: H04B1/58 , H03K19/0175 , H04L25/02
Abstract: A bidirectional data link includes a forward channel transmitter circuit and a forward channel receiver circuit. The forward channel transmitter circuit includes a forward channel driver circuit, and a back channel receiver circuit. The back channel receiver circuit is coupled to the forward channel driver circuit. The back channel receiver circuit includes a summation circuit and an active filter circuit. The summation circuit is coupled to the forward channel driver circuit. The active filter circuit is coupled to the summation circuit. The forward channel receiver circuit includes a forward channel receiver, and a back channel driver circuit. The back channel driver circuit is coupled to the forward channel receiver.
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公开(公告)号：US20240163138A1
公开(公告)日：2024-05-16
申请号：US18419653
申请日：2024-01-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abishek MANIAN , Nithin Sathisan PODUVAL , Roland Nii Ofei RIBEIRO
CPC classification number: H04L25/03057 , H03K3/0372
Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.
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Patent Agency Ranking
公开(公告)号：US20230122240A1
公开(公告)日：2023-04-20
申请号：US18066027
申请日：2022-12-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abishek MANIAN , Nithin Sathisan PODUVAL , Roland Nii Ofei RIBEIRO
Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.
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公开(公告)号：US20210409248A1
公开(公告)日：2021-12-30
申请号：US17083008
申请日：2020-10-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abishek MANIAN , Amit RANE , Ashwin Kottilvalappil VIJAYAN
Abstract: A linear retimer includes an equalizer, a clock recovery circuit, a sample and hold (S/H) circuit, and a linear driver. The equalizer receives an input signal and outputs an equalized signal. The clock recovery circuit receives the equalized signal and outputs a clock signal. The S/H circuit receives the equalized signal and the clock signal and outputs a retimed signal. The linear driver receives the retimed signal and outputs a recovered signal. The S/H circuit is configured to preserve a voltage of the equalized signal in the retimed signal. In some examples, the S/H circuit is part of a linear three-tap feedforward equalizer, and the linear driver receives an output of the feedforward equalizer. The linear retimer can be placed between a transmitter and a channel or after the channel.
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公开(公告)号：US20210409246A1
公开(公告)日：2021-12-30
申请号：US17095869
申请日：2020-11-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abishek MANIAN , Ashwin Kottilvalappil VIJAYAN , Amit RANE , Ashkan ROSHAN ZAMIR
Abstract: An N-tap feedforward equalizer (FFE) comprises a set of N FFE taps coupled together in parallel, a filter coupled between the (N−1)th FFE tap and the Nth FFE tap, and a summer coupled to an output of the set of N FFE taps. Each FFE tap includes a unique sample-an-hold (S/H) circuit that generates a unique time-delayed signal and a unique transconductance stage that generates a unique transconductance output based on the unique time-delayed signal. The filter causes the N-tap FFE to have the behavior of greater than N taps. In some examples, the filter is a first order high pass filter that causes coefficients greater than N to have an opposite polarity of the Nth coefficient. In some examples, the filter is a first order low pass filter that causes coefficients greater than N to have the same polarity as the Nth coefficient.
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公开(公告)号：US20240235804A9
公开(公告)日：2024-07-11
申请号：US18309587
申请日：2023-04-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abishek MANIAN , Ashkan ROSHAN ZAMIR , Yonghui TANG , Robin GUPTA , Michael G. VRAZEL
CPC classification number: H04L7/0016 , H04L25/03012
Abstract: A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.
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公开(公告)号：US20220286327A1
公开(公告)日：2022-09-08
申请号：US17193067
申请日：2021-03-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abishek MANIAN , Nithin Sathisan PODUVAL , Roland Nii Ofei RIBEIRO
Abstract: An error sampler circuit includes a differential input voltage input, a differential reference voltage input, a master latch circuit, and a slave latch circuit. The master latch circuit includes a slicer circuit. The slicer circuit includes a first input, a second input, and a differential output. The first input is coupled to the differential input voltage input. The second input is coupled to the differential reference voltage input. The slave latch includes a differential input coupled to the differential output of the slicer circuit.
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