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公开(公告)号：US11201547B2
公开(公告)日：2021-12-14
申请号：US16407493
申请日：2019-05-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Philomena Cleopha Brady , Ananthakrishnan Viswanathan , Shanguang Xu
Abstract: A switching converter is provided that includes a power MOSFET, a controller having a drive pin connected to a gate terminal of the power MOSFET, and a resistor connected to the gate terminal. A compensation time selection circuit is included that has compensation times stored therein. A compensation time is selected from the compensation times based on a value of the resistor and stored in the controller. The selected compensation time compensates for an inherent delay in switching the power MOSFET to an ON state after the power MOSFET receives a signal to switch to the ON state to allow the power MOSFET to switch to the ON state when a drain voltage of the power MOSFET's reaches its lowest value during a switching cycle.
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公开(公告)号：US10186964B1
公开(公告)日：2019-01-22
申请号：US15943415
申请日：2018-04-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Michael Ryan Hanschke , Salvatore Giombanco , John C. Vogt , Filippo Marino , Joseph Michael Leisten , Ananthakrishnan Viswanathan
Abstract: At least some aspects of the present disclosure provide for a circuit. In one example, the circuit includes a logic circuit having multiple inputs and multiple outputs, a calculated discontinuous conduction (DCM) (TDCM) timer having an input coupled to one of the logic circuit outputs and an output coupled to one of the logic circuit inputs, an on-time (TON) timer having an input coupled to one of the logic circuit outputs and an output coupled to one of the logic circuit inputs, and a hysteresis timer having an input coupled to one of the logic circuit outputs and multiple outputs coupled to multiple of the logic circuit inputs.
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公开(公告)号：US10411592B2
公开(公告)日：2019-09-10
申请号：US15854467
申请日：2017-12-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ananthakrishnan Viswanathan , Salvatore Giombanco , Joseph Michael Leisten , Philomena Cleopha Brady
Abstract: A power factor correction circuit includes a power transistor, an inductor, and detection circuitry. The inductor is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to the drain terminal of the power transistor. The detection circuitry is configured to determine an input voltage applied to the inductor based on resonant ringing of voltage at the drain terminal, and to detect a valley in the voltage at the drain terminal based on the input voltage applied to the inductor.
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公开(公告)号：US20190356219A1
公开(公告)日：2019-11-21
申请号：US16525790
申请日：2019-07-30
Applicant: Texas Instruments Incorporated
Inventor： Ananthakrishnan Viswanathan , Salvatore Giombanco , Joseph Michael Leisten , Philomena Cleopha Brady
Abstract: A power factor correction circuit includes a power transistor, an inductor, and detection circuitry. The inductor is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to the drain terminal of the power transistor. The detection circuitry is configured to determine an input voltage applied to the inductor based on resonant ringing of voltage at the drain terminal, and to detect a valley in the voltage at the drain terminal based on the input voltage applied to the inductor.
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公开(公告)号：US20190267903A1
公开(公告)日：2019-08-29
申请号：US16407493
申请日：2019-05-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Philomena Cleopha Brady , Ananthakrishnan Viswanathan , Shanguang Xu
Abstract: A switching converter is provided that includes a power MOSFET, a controller having a drive pin connected to a gate terminal of the power MOSFET, and a resistor connected to the gate terminal. A compensation time selection circuit is included that has compensation times stored therein. A compensation time is selected from the compensation times based on a value of the resistor and stored in the controller. The selected compensation time compensates for an inherent delay in switching the power MOSFET to an ON state after the power MOSFET receives a signal to switch to the ON state to allow the power MOSFET to switch to the ON state when a drain voltage of the power MOSFET's reaches its lowest value during a switching cycle.
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Patent Agency Ranking
公开(公告)号：US10326373B1
公开(公告)日：2019-06-18
申请号：US15874697
申请日：2018-01-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Philomena Cleopha Brady , Ananthakrishnan Viswanathan , Shanguang Xu
CPC classification number: H02M3/33515 , H02M1/08 , H02M1/42 , H02M2001/0054
Abstract: A switching converter is provided that includes a power MOSFET, a controller having a drive pin connected to a gate terminal of the power MOSFET, and a resistor connected to the gate terminal. A compensation time selection circuit is included that has compensation times stored therein. A compensation time is selected from the compensation times based on a value of the resistor and stored in the controller. The selected compensation time compensates for an inherent delay in switching the power MOSFET to an ON state after the power MOSFET receives a signal to switch to the ON state to allow the power MOSFET to switch to the ON state when a drain voltage of the power MOSFET's reaches its lowest value during a switching cycle.
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公开(公告)号：US10128744B1
公开(公告)日：2018-11-13
申请号：US15840318
申请日：2017-12-13
Applicant: Texas Instruments Incorporated
Inventor： Ananthakrishnan Viswanathan , Joseph Michael Leisten , Brent McDonald , Philomena Cleopha Brady
IPC: H02M1/42
Abstract: Disclosed examples include methods and control circuits to operate a single or multi-phase DC-DC converter, including an output that turns a first switch on for a controlled on time and then turns the switch off for a controlled off time in successive control cycles, as well as a PWM circuit that computes a threshold time value corresponding to a predetermined peak inductor current and a duty cycle value, and computes a first time value according to an error value for a subsequent second switching control cycle. The PWM circuit sets the on time to the first time value to operate in a critical conduction mode for the second switching control cycle when the first time value is greater than or equal to the threshold time value, and otherwise sets the controlled on time to the threshold time value for discontinuous conduction mode operation in the second control cycle.
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公开(公告)号：US10756620B2
公开(公告)日：2020-08-25
申请号：US16525790
申请日：2019-07-30
Applicant: Texas Instruments Incorporated
Inventor： Ananthakrishnan Viswanathan , Salvatore Giombanco , Joseph Michael Leisten , Philomena Cleopha Brady
Abstract: A power factor correction circuit includes a power transistor, an inductor, and detection circuitry. The inductor is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to the drain terminal of the power transistor. The detection circuitry is configured to determine an input voltage applied to the inductor based on resonant ringing of voltage at the drain terminal, and to detect a valley in the voltage at the drain terminal based on the input voltage applied to the inductor.
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公开(公告)号：US10673322B1
公开(公告)日：2020-06-02
申请号：US16544425
申请日：2019-08-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Salvatore Giombanco , Ananthakrishnan Viswanathan , William James Long
Abstract: A power factor correction controller zero current detection circuit includes a differentiator circuit, a comparator, a first qualification timer circuit, an idle ringing detector circuit, a second qualification timer circuit, and a flip-flop. The comparator is coupled to the differentiator circuit. The first qualification timer circuit includes an input coupled to an output of the comparator. The idle ringing detector circuit includes a first input coupled to the output of the comparator, and a second input coupled to an output of the first qualification timer circuit. The second qualification timer circuit includes a first input coupled to the output of the first qualification timer circuit, and a second input coupled an output of the idle ringing detector circuit. The flip-flop includes a first input coupled to the output of the comparator, and a second input coupled to an output of the second qualification timer circuit.
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公开(公告)号：US10284077B1
公开(公告)日：2019-05-07
申请号：US15785757
申请日：2017-10-17
Applicant: Texas Instruments Incorporated
Inventor： Joseph Michael Leisten , Ananthakrishnan Viswanathan , Philomena Cleopha Brady , Brent Alan McDonald
Abstract: A Power Factor Correction (PFC) controller includes an error amplifier for amplifying a difference between Vout and intended Vout to provide a power demand (Pdem) output at a compensation pin. A burst mode controller includes soft-start circuitry coupled to receive Pdem and to a drive pin which provides pulses to a control node of a power switch of a DC-DC converter during burst periods. The pulses slow ramping of line current over a first 2 to 36 switching cycles at a beginning of bursts when energizing the inductor to reduce a line current slope as compared to without ramping up, and for slowing ramping down of line current over the last 2 to 36 switching cycles to reduce a line current slope when de-energizing the inductor as compared to a line current without ramping down. The PFC controller does not utilize zero-crossings of the line voltage for burst period synchronization.
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