公开(公告)号：US20240103811A1

公开(公告)日：2024-03-28

申请号：US18355795

申请日：2023-07-20

Applicant: Texas Instruments Incorporated

Inventor： Mahesh M Mehendale ,  Atul Lele ,  Nagendra Gulur ,  Hetul Sanghvi ,  Srinivasa BS Chakravarthy

IPC: G06F7/544 ,  G06N3/0464

CPC classification number: G06F7/5443 ,  G06N3/0464

Abstract: In one example, a neural network processor comprises an input data register, a weights register, a computing engine configurable to perform multiplication and accumulation (MAC) operations between input data elements of a range of input precisions and weight elements of a range of weight precisions, and a controller. The controller is configured to: receive a first indication of the particular input precision and a second indication of the particular weight precision, and configure the computing engine based on the first and second indications. The controller is also configured to, responsive to an instruction: fetch input data elements and weight elements to the computing engine; and perform, using the computing engine configured based on the first and second indications, MAC operations between the input data elements at the particular input precision and the weight elements at the particular weight precision to generate intermediate output data elements.

公开(公告)号：US20250077230A1

公开(公告)日：2025-03-06

申请号：US18643336

申请日：2024-04-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Atul Lele ,  Mahesh Mehendale ,  Uri Weinrib ,  Anurag Choudhury

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed herein are improvements to instructions and hardware for performing neural network operations. In an embodiment, a processing device includes instruction fetch circuitry, decoder circuitry, and neural network operation circuitry. The instruction fetch circuitry is configured to fetch a neural network instruction from memory that specifies an operation and a set of values that enable sub-circuits of the neural network operation circuitry for use with one or more of the operations of the group of operations and provide the neural network instruction to the decoder circuitry. The decoder circuitry is configured to cause the neural network operation circuitry to perform, based on the operation, a convolution operation using a first sub-circuit of the neural network operation circuitry and a first subset of the set of values or a batch normalization operation using a second sub-circuit of the neural network operation circuitry and a second subset of the set of values.

公开(公告)号：US20240104361A1

公开(公告)日：2024-03-28

申请号：US18355749

申请日：2023-07-20

Applicant: Texas Instruments Incorporated

Inventor： Mahesh M Mehendale ,  Hetul Sanghvi ,  Nagendra Gulur ,  Atul Lele ,  Srinivasa BS Chakravarthy

IPC: G06N3/063 ,  G06N3/048

CPC classification number: G06N3/063 ,  G06N3/048

Abstract: In one example, a neural network processor comprises a computing engine and a post-processing engine, the post-processing engine configurable to perform different post-processing operations for a range of output precisions and a range of weight precisions. The neural network processor further comprises a controller configured to: receive a first indication of a particular output precision, a second indication of the particular weight precision, and post-processing parameters; and configure the post-processing engine based on the first and second indications and the first and second post-processing parameters. The controller is further configured to, responsive to a first instruction, perform, using the computing engine, multiplication and accumulation operations between input data elements and weight elements to generate intermediate data elements. The controller is further configured to, responsive to a second instruction, perform, using the configured post-processing engine, post-processing operations on the intermediate data elements to generate output data elements.

公开(公告)号：US20240103875A1

公开(公告)日：2024-03-28

申请号：US18355689

申请日：2023-07-20

Applicant: Texas Instruments Incorporated

Inventor： Mahesh M Mehendale ,  Nagendra Gulur ,  Srinivasa BS Chakravarthy ,  Atul Lele ,  Hetul Sanghvi

IPC: G06F9/38 ,  G06F9/30 ,  G06N3/063

CPC classification number: G06F9/3814 ,  G06F9/3004 ,  G06N3/063

Abstract: In one example, a neural network processor comprises a memory interface, an instruction buffer, a weights buffer, an input data register, a weights register, an output data register, a computing engine, and a controller. The controller is configured to: receive a first instruction from the instruction buffer; responsive to the first instruction, fetch input data elements from the memory interface to the input data register, and fetch weight elements from the weights buffer to the weights register. The controller is also configured to: receive a second instruction from the instruction buffer; and responsive to the second instruction: fetch the input data elements and the weight elements from, respectively, the input data register and the weights register to the computing engine; and perform, using the computing engine, computation operations between the input data elements and the weight elements to generate output data elements.