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    INTEGRATED CIRCUIT DEVICE WITH IMPROVED OXIDE EDGING
    1.
    发明申请
    INTEGRATED CIRCUIT DEVICE WITH IMPROVED OXIDE EDGING 有权

    公开(公告)号：US20230135889A1

    公开(公告)日：2023-05-04

    申请号：US17514786

    申请日：2021-10-29

    Applicant: Texas Instruments Incorporated

    Inventor： Abbas Ali ,  Christopher Scott Whitesell ,  John Christopher Shriner ,  Henry Litzmann Edwards

    IPC: H01L21/762 ,  H01L27/06 ,  H01L29/78 ,  H01L29/66

    Abstract: A method of forming an integrated circuit forms a first oxygen diffusion barrier layer in a fixed position relative to a semiconductor substrate and forms an aperture through the first oxygen diffusion barrier layer to expose a portion of the semiconductor substrate. The method also forms a first LOCOS region in an area of the aperture and a second oxygen diffusion barrier layer along the first LOCOS region and along at least a sidewall portion of the first oxygen diffusion barrier layer in the area of the aperture. The method also deposits a polysilicon layer, at a temperature of 570° C. or less, over the second oxygen diffusion barrier layer, etches the polysilicon layer and the second oxygen diffusion barrier layer to form a spacer in the area of the aperture, and forms a second LOCOS region in the area of the aperture and aligned to the spacer.

    Control of locos structure thickness without a mask
    3.
    发明授权
    Control of locos structure thickness without a mask 有权

    公开(公告)号：US11984362B1

    公开(公告)日：2024-05-14

    申请号：US17411761

    申请日：2021-08-25

    Applicant: Texas Instruments Incorporated

    Inventor： Abbas Ali ,  Christopher Scott Whitesell ,  John Christopher Shriner ,  Henry Litzmann Edwards

    IPC: H01L21/8234 ,  H01L27/088

    CPC classification number: H01L21/823462 ,  H01L27/088

    Abstract: A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

    GATE OXIDE FABRICATION AND SYSTEM
    5.
    发明申请
    GATE OXIDE FABRICATION AND SYSTEM 有权

    公开(公告)号：US20230087463A1

    公开(公告)日：2023-03-23

    申请号：US17483286

    申请日：2021-09-23

    Applicant: Texas Instruments Incorporated

    Inventor： Mona M. Eissa ,  Corinne Ann Gagnet ,  Christopher Scott Whitesell ,  Pushpa Mahalingam

    IPC: H01L21/02

    Abstract: A method of forming an integrated circuit, including first, positioning a semiconductor wafer in a processing chamber; second, exposing portions of the semiconductor wafer, including introducing a first amount of hydrogen into the processing chamber and introducing a first amount of oxygen into the processing chamber; and, third, introducing at least one of a second amount of hydrogen or a second amount of oxygen into the processing chamber, the second amount of hydrogen greater than zero and less than the first amount of hydrogen and the second amount of oxygen greater than zero and less than the first amount of oxygen.

    CONTROL OF LOCOS STRUCTURE THICKNESS WITHOUT A MASK
    6.
    发明公开
    CONTROL OF LOCOS STRUCTURE THICKNESS WITHOUT A MASK 审中-公开

    公开(公告)号：US20240258175A1

    公开(公告)日：2024-08-01

    申请号：US18632439

    申请日：2024-04-11

    Applicant: Texas Instruments Incorporated

    Inventor： Abbas Ali ,  Christopher Scott Whitesell ,  John Christopher Shriner ,  Henry Litzmann Edwards

    IPC: H01L21/8234 ,  H01L27/088

    CPC classification number: H01L21/823462 ,  H01L27/088

    Abstract: A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

    Gate oxide fabrication and system
    7.
    发明授权
    Gate oxide fabrication and system 有权

    公开(公告)号：US11972942B2

    公开(公告)日：2024-04-30

    申请号：US17483286

    申请日：2021-09-23

    Applicant: Texas Instruments Incorporated

    Inventor： Mona M. Eissa ,  Corinne Ann Gagnet ,  Christopher Scott Whitesell ,  Pushpa Mahalingam

    IPC: H01L21/02

    CPC classification number: H01L21/02236 ,  H01L21/02164 ,  H01L21/02255

    Abstract: A method of forming an integrated circuit, including first, positioning a semiconductor wafer in a processing chamber; second, exposing portions of the semiconductor wafer, including introducing a first amount of hydrogen into the processing chamber and introducing a first amount of oxygen into the processing chamber; and, third, introducing at least one of a second amount of hydrogen or a second amount of oxygen into the processing chamber, the second amount of hydrogen greater than zero and less than the first amount of hydrogen and the second amount of oxygen greater than zero and less than the first amount of oxygen.

    Method of annealing out silicon defectivity
    9.
    发明公开
    Method of annealing out silicon defectivity 审中-公开

    公开(公告)号：US20230215737A1

    公开(公告)日：2023-07-06

    申请号：US17566942

    申请日：2021-12-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Abbas Ali ,  Christopher Scott Whitesell ,  Pushpa Mahalingam ,  Uma Aghoram ,  Eddie Dee Pylant

    IPC: H01L21/322

    CPC classification number: H01L21/322 ,  H01L21/76224

    Abstract: A method of forming an integrated circuit that includes placing a semiconductor substrate in a process chamber at an initial temperature, wherein one or more trenches are located within the semiconductor substrate. The temperature of the substrate is increased in a substantially oxygen-free ambient to an oxide-growth temperature. The temperature is then maintained at the oxide growth temperature while providing an oxidizing ambient, thereby forming an oxide layer on sidewalls of the trench. The temperature of the semiconductor wafer is then reduced to a final temperature below the initial temperature and removed from the process chamber.

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