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    MOS transistors including SiON gate dielectric with enhanced nitrogen concentration at its sidewalls
    4.
    发明授权
    MOS transistors including SiON gate dielectric with enhanced nitrogen concentration at its sidewalls 有权
    MOS晶体管包括在其侧壁处具有增强的氮浓度的SiON栅极电介质

    公开(公告)号：US08748992B2

    公开(公告)日：2014-06-10

    申请号：US13856702

    申请日：2013-04-04

    Applicant: Texas Instruments Incorporated

    Inventor： Brian K. Kirkpatrick ,  James Joseph Chambers

    IPC: H01L21/70 ,  H01L29/78 ,  H01L29/51

    CPC classification number: H01L29/518 ,  H01L21/28044 ,  H01L21/28202 ,  H01L29/78

    Abstract: A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ≧ the N concentration in a bulk of the annealed N-enhanced SiON gate layer −2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack.

    Abstract translation: 形成具有至少一个MOS器件的集成电路（IC）的方法包括在硅表面上形成SiON栅介质层。 在SiON栅极层上沉积栅电极层，然后构图形成栅叠层。 通过图案化揭示了暴露的栅极电介质侧壁。 在暴露的SiON侧壁上形成补充的氧化硅层，然后氮化。 氮化后，后氮化退火（PNA）形成包括N增强SiON侧壁的退火的N增强SiON栅极电介质层，其中沿着恒定厚度的线，N增强SiON侧壁处的N浓度为≥N 大部分退火的N增强SiON栅极层为-2原子％。 形成栅极堆叠的相对侧上的源极和漏极区域以限定栅极叠层下方的沟道区域。

    Inner L-spacer for replacement gate flow
    7.
    发明授权
    Inner L-spacer for replacement gate flow 有权
    内部L型间隔器用于更换浇口流

    公开(公告)号：US09087917B2

    公开(公告)日：2015-07-21

    申请号：US14022317

    申请日：2013-09-10

    Applicant: Texas Instruments Incorporated

    Inventor： Chet Vernon Lenox ,  Seung-Chul Song ,  Brian K. Kirkpatrick

    IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8234 ,  H01L27/092

    CPC classification number: H01L21/823864 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66553

    Abstract: An integrated circuit is formed by removing a sacrificial gate dielectric layer and a sacrificial gate to form a gate cavity. A conformal dielectric first liner is formed in the gate cavity and a conformal second liner is formed on the first liner. A first etch removes the second liner from the bottom of the gate cavity, leaving material of the second liner on sidewalls of the gate cavity. A second etch removes the first liner from the bottom of the gate cavity exposed by the second liner, leaving material of the first liner on the bottom of the gate cavity under the second liner on the sidewalls of the gate cavity. A third etch removes the second liner from the gate cavity, leaving an L-shaped spacers of the first liner in the gate cavity. A permanent gate dielectric layer and replacement gate are formed in the gate cavity.

    Abstract translation: 通过去除牺牲栅极电介质层和牺牲栅极以形成栅极腔来形成集成电路。 在栅腔中形成保形电介质第一衬垫，并且在第一衬垫上形成共形第二衬垫。 第一蚀刻从栅极腔的底部去除第二衬垫，使第二衬垫的材料留在栅腔的侧壁上。 第二蚀刻从第二衬垫暴露的栅腔的底部去除第一衬垫，在栅腔的侧壁上的第二衬垫下方留下第一衬垫的底部上的第一衬垫的底部的材料。 第三蚀刻从栅极腔去除第二衬垫，在栅极腔中留下第一衬里的L形间隔物。 永久性栅极介电层和置换栅极形成在栅极腔中。

    SPLIT GATE MEMORY CELL FABRICATION AND SYSTEM
    8.
    发明申请
    SPLIT GATE MEMORY CELL FABRICATION AND SYSTEM 审中-公开

    公开(公告)号：US20200381541A1

    公开(公告)日：2020-12-03

    申请号：US16426222

    申请日：2019-05-30

    Applicant: Texas Instruments Incorporated

    Inventor： John Howard MacPeak ,  Douglas Ticknor Grider ,  Brian K. Kirkpatrick

    IPC: H01L29/66 ,  H01L29/40 ,  H01L21/311

    Abstract: A method of forming an integrated circuit relative to a wafer comprising a semiconductor substrate. The method first forms a first dielectric layer having a first thickness and along the substrate, the first forming step comprising plasma etching the wafer in a first substrate area and a second substrate area and thereafter growing the first dielectric layer in the first substrate area and the second substrate area. After the first step, the method second forms a second dielectric layer having a second thickness and along the substrate in the second substrate area, the second thickness less than the first thickness, the second forming step comprising removal of the first dielectric layer in the second substrate area without plasma and until a surface of the substrate is exposed and growing the second dielectric layer in at least a portion of the surface.

    Method of fabricating semiconductors
    10.
    发明授权
    Method of fabricating semiconductors 有权
    半导体制造方法

    公开(公告)号：US09490143B1

    公开(公告)日：2016-11-08

    申请号：US14952693

    申请日：2015-11-25

    Applicant: Texas Instruments Incorporated

    Inventor： David Gerald Farber ,  Ping Jiang ,  Brian K. Kirkpatrick ,  Douglas T. Grider, III

    IPC: H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/02

    CPC classification number: H01L21/28123 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/823462

    Abstract: A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.

    Abstract translation: 制造半导体的方法包括将平坦化材料施加到基板并在平坦化材料中形成开口。 开口充满了多晶硅。 多个蚀刻调制序列被施加到衬底，每个蚀刻调制序列包括：对衬底施加第一蚀刻工艺，其中第一蚀刻工艺比平坦化材料对多晶硅更有选择性; 以及对所述衬底施加第二蚀刻工艺，其中所述第二蚀刻工艺对所述平坦化材料比所述多晶硅更具选择性。

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