公开(公告)号：US12212317B2

公开(公告)日：2025-01-28

申请号：US18131009

申请日：2023-04-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Erkan Bilhan ,  Francisco A. Cano

IPC: H03K19/003 ,  H03K19/20

Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

公开(公告)号：US11831309B2

公开(公告)日：2023-11-28

申请号：US16378742

申请日：2019-04-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Erkan Bilhan ,  Francisco A. Cano

IPC: H03K19/003 ,  H03K19/20 ,  H03K3/356

CPC classification number: H03K19/00315 ,  H03K3/356113 ,  H03K19/20

Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is coupled to the second current terminal at an intermediate node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

公开(公告)号：US20230238959A1

公开(公告)日：2023-07-27

申请号：US18131009

申请日：2023-04-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Erkan Bilhan ,  Francisco A. Cano

IPC: H03K19/003 ,  H03K19/20

CPC classification number: H03K19/00315 ,  H03K19/20

Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

公开(公告)号：US20240088896A1

公开(公告)日：2024-03-14

申请号：US18516256

申请日：2023-11-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Erkan Bilhan ,  Francisco A. Cano

IPC: H03K19/003 ,  H03K3/356 ,  H03K19/20

CPC classification number: H03K19/00315 ,  H03K3/356113 ,  H03K19/20

Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is coupled to the second current terminal at an intermediate node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.

公开(公告)号：US11626875B2

公开(公告)日：2023-04-11

申请号：US16262327

申请日：2019-01-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Erkan Bilhan ,  Francisco A. Cano

IPC: H03K19/003 ,  H03K19/20

Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.