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1.发明授权公开(公告)号：US11269389B2
公开(公告)日：2022-03-08
申请号：US16814625
申请日：2020-03-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkateswar Reddy Kowkutla , Chunhua Hu , Erkan Bilhan , Sumant Dinkar Kale
Abstract: A functional safety POR system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. Three stages of voltage monitoring are implemented to ensure redundancy.
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公开(公告)号：US10574235B2
公开(公告)日：2020-02-25
申请号：US16284212
申请日：2019-02-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
IPC: H03K19/0175 , H03K3/037
Abstract: A method and circuitry that enables an input/output pin (I/O) on a System on a Chip to function either as an analog or as a digital input/output without compromising the overall performance of the system, thus giving the automated test equipment full flexibility to maximize parallel testing for both analog and digital modules.
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3.发明授权Sourcing and securing dual supply rails of tamper protected battery backed domain 有权采购和保护篡改电池支持域的双电源轨公开(公告)号：US09231409B2
公开(公告)日：2016-01-05
申请号：US13744664
申请日：2013-01-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Erkan Bilhan
CPC classification number: H02J4/00 , G06F1/26 , G06F21/86 , Y10T307/383
Abstract: This invention is a System On a Chip (SOC) requiring two tamper resistant externally generated power supplies. A first, higher power supply powers I/O and analog circuits. A second, lower power supply powers digital circuits and memory. A first voltage monitor circuit powered by said first power supply generates a first output signal when the first power supply is below an operational limit high level. A second voltage monitor circuit powered by said first power supply indicates when the second power supply is above an operational high limit level. A power switch is controlled by the first voltage monitor circuit. This power switch connects the second power supply and second load when closed and isolates them when open. Thus the memory cannot be accessed when the I/O and analog power supply is out of specification.
Abstract translation: 本发明是一种片上系统（SOC），需要两个防篡改外部产生的电源。 第一个更高的电源为I / O和模拟电路供电。 第二个较低的电源为数字电路和存储器供电。 当第一电源低于操作极限高电平时，由所述第一电源供电的第一电压监视器电路产生第一输出信号。 由所述第一电源供电的第二电压监视器电路指示第二电源何时高于操作上限电平。 电源开关由第一电压监视电路控制。 此电源开关在关闭时连接第二个电源和第二个负载，并在打开时将其隔离。 因此，当I / O和模拟电源超出规格时，无法访问存储器。
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公开(公告)号：US20240178832A1
公开(公告)日：2024-05-30
申请号：US18432430
申请日：2024-02-05
Applicant: Texas Instruments Incorporated
Inventor： Venkateswar Reddy Kowkutla , Chunhua Hu , Erkan Bilhan , Sumant Dinkar Kale
IPC: H03K17/22 , G05B19/042 , G06F1/24 , G06F1/3296 , H03K17/30
CPC classification number: H03K17/22 , G05B19/042 , G06F1/24 , G06F1/3296 , G05B2219/21119 , H03K17/30
Abstract: Systems and methods are provided for voltage monitoring and reset sequencing. One such system includes a voltage detector including multiple voltage level detectors to output multiple power OK signals, respectively; a trim adjustment circuit to output multiple trim values to the multiple voltage level detectors, respectively; and a sequencer circuit coupled to the trim adjustment circuit and the voltage detector. In response to receiving the power OK signals from the multiple voltage level detectors, the sequencer circuit controls output of a reset signal to a target voltage domain.
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公开(公告)号：US11923836B2
公开(公告)日：2024-03-05
申请号：US16912057
申请日：2020-06-25
Applicant: Texas Instruments Incorporated
Inventor： Venkateswar Reddy Kowkutla , Chunhua Hu , Erkan Bilhan , Sumant Dinkar Kale
IPC: H03K17/22 , G05B19/042 , G06F1/24 , G06F1/3296 , H03K17/30
CPC classification number: H03K17/22 , G05B19/042 , G06F1/24 , G06F1/3296 , G05B2219/21119 , H03K17/30
Abstract: An example includes a circuit including a first AND gate including a first input terminal, a second input terminal, and an output terminal, a second AND gate including a first input terminal, a second input terminal, and an output terminal, and a third AND gate including a first input terminal, a second input terminal, and an output terminal. The circuit also includes an OR gate including a first input terminal coupled to the output terminal of the first AND gate, a second input terminal coupled to the output terminal of the second AND gate, a third input terminal coupled to the output terminal of the third AND gate, and an output terminal.
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Patent Agency Ranking
公开(公告)号：US10050617B2
公开(公告)日：2018-08-14
申请号：US15387683
申请日：2016-12-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkateswar Reddy Kowkutla , Erkan Bilhan , Sumant Dinkar Kale , Chunhua Hu
Abstract: A functional safety Power on Reset system requires implementing voltage detectors and supervisory functions in a complex SOC. These features are implemented within the SOC without external components. A plurality of voltage monitoring stages is implemented to ensure redundancy.
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公开(公告)号：US12212317B2
公开(公告)日：2025-01-28
申请号：US18131009
申请日：2023-04-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Erkan Bilhan , Francisco A. Cano
IPC: H03K19/003 , H03K19/20
Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.
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公开(公告)号：US11831309B2
公开(公告)日：2023-11-28
申请号：US16378742
申请日：2019-04-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Erkan Bilhan , Francisco A. Cano
IPC: H03K19/003 , H03K19/20 , H03K3/356
CPC classification number: H03K19/00315 , H03K3/356113 , H03K19/20
Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is coupled to the second current terminal at an intermediate node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.
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公开(公告)号：US20230238959A1
公开(公告)日：2023-07-27
申请号：US18131009
申请日：2023-04-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Erkan Bilhan , Francisco A. Cano
IPC: H03K19/003 , H03K19/20
CPC classification number: H03K19/00315 , H03K19/20
Abstract: A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is connected to the second current terminal at an intermediate node and the fourth current terminal connected to a ground or supply node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.
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公开(公告)号：US11132659B2
公开(公告)日：2021-09-28
申请号：US14799341
申请日：2015-07-14
Applicant: Texas Instruments Incorporated
Inventor： Erkan Bilhan , Rajitha Padakanti , Amritpal Singh Mundra
Abstract: A financial transaction system includes sensors, a tamper detection module, and circuitry configurable to control which sensors are used, and the circuitry is configurable after the tamper detection module has been manufactured.
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