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公开(公告)号：US09706229B2
公开(公告)日：2017-07-11
申请号：US13950042
申请日：2013-07-24
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Chaitanya S Ghone , Joseph Meehan
Abstract: A VP8 video decoder is implemented by partitioning the required functions across multiple sub systems, with an optimal mapping to existing functional blocks. Key optimizations include the reuse of hardware designed for prior generation V^6 and VP7 decoders. In order to reduce implementation complexity, cost and power consumption, a non exact, approximate deblocking loop filter is implemented.
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公开(公告)号：US20210337242A1
公开(公告)日：2021-10-28
申请号：US17367387
申请日：2021-07-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra Mody , Chaitanya S. Ghone , Joseph Meehan
Abstract: A video decoder system, in one embodiment, includes one or more processors and a memory storing instructions that when executed by the one or more processors cause the video decoding system to perform an entropy decoding operation in a frame level pipelined manner on a bitstream representative of encoded video data to produce first output data, perform at least one of an inverse quantization operation or an inverse frequency transform operation in a row level pipelined manner on the first output data to produce second output data, perform a deblocking filtering operation on first input data that includes the second output data in a row level pipelined manner to produce third output data, and output a decoded video output based on the third output data.
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公开(公告)号：US20170311002A1
公开(公告)日：2017-10-26
申请号：US15646258
申请日：2017-07-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra Mody , Chaitanya S Ghone , Joseph Meehan
Abstract: A VP8 video decoder is implemented by partitioning the required functions across multiple sub systems, with an optimal mapping to existing functional blocks. Key optimizations include the reuse of hardware designed for prior generation V̂6 and VP7 decoders. In order to reduce implementation complexity, cost and power consumption, a non exact, approximate deblocking loop filter is implemented.
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Patent Agency Ranking
公开(公告)号：US11115683B2
公开(公告)日：2021-09-07
申请号：US16432317
申请日：2019-06-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra Mody , Chaitanya S. Ghone , Joseph Meehan
Abstract: A video decoder system, in one embodiment, includes one or more processors and a memory storing instructions that when executed by the one or more processors cause the video decoding system to perform an entropy decoding operation in a frame level pipelined manner on a bitstream representative of encoded video data to produce first output data, perform at least one of an inverse quantization operation or an inverse frequency transform operation in a row level pipelined manner on the first output data to produce second output data, perform a deblocking filtering operation on first input data that includes the second output data in a row level pipelined manner to produce third output data, and output a decoded video output based on the third output data.
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公开(公告)号：US20190289333A1
公开(公告)日：2019-09-19
申请号：US16432317
申请日：2019-06-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra Mody , Chaitanya S. Ghone , Joseph Meehan
Abstract: A video decoder system, in one embodiment, includes one or more processors and a memory storing instructions that when executed by the one or more processors cause the video decoding system to perform an entropy decoding operation in a frame level pipelined manner on a bitstream representative of encoded video data to produce first output data, perform at least one of an inverse quantization operation or an inverse frequency transform operation in a row level pipelined manner on the first output data to produce second output data, perform a deblocking filtering operation on first input data that includes the second output data in a row level pipelined manner to produce third output data, and output a decoded video output based on the third output data.
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公开(公告)号：US20140362928A1
公开(公告)日：2014-12-11
申请号：US13950042
申请日：2013-07-24
Applicant: Texas Instruments Incorporated
Inventor： Mihir Narendra Mody , Chaitanya S. Ghone , Joseph Meehan
IPC: H04N19/86 , H04N19/593 , H04N19/503 , H04N19/44 , H04N19/91
Abstract: A VP8 video decoder is implemented by partitioning the required functions across multiple sub systems, with an optimal mapping to existing functional blocks. Key optimizations include the reuse of hardware designed for prior generation V̂6 and VP7 decoders. In order to reduce implementation complexity, cost and power consumption, a non exact, approximate deblocking loop filter is implemented.
Abstract translation: VP8视频解码器通过跨多个子系统划分所需的功能，并与现有的功能块进行最佳映射来实现。 关键优化包括为先前的V6和VP7解码器设计的硬件的重用。 为了降低实现的复杂性，成本和功耗，实现了非精确的近似去块环路滤波器。
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公开(公告)号：US12256108B2
公开(公告)日：2025-03-18
申请号：US17367387
申请日：2021-07-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra Mody , Chaitanya S. Ghone , Joseph Meehan
Abstract: A video decoder system, in one embodiment, includes one or more processors and a memory storing instructions that when executed by the one or more processors cause the video decoding system to perform an entropy decoding operation in a frame level pipelined manner on a bitstream representative of encoded video data to produce first output data, perform at least one of an inverse quantization operation or an inverse frequency transform operation in a row level pipelined manner on the first output data to produce second output data, perform a deblocking filtering operation on first input data that includes the second output data in a row level pipelined manner to produce third output data, and output a decoded video output based on the third output data.
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公开(公告)号：US10321163B2
公开(公告)日：2019-06-11
申请号：US15646258
申请日：2017-07-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Mihir Narendra Mody , Chaitanya S Ghone , Joseph Meehan
Abstract: A VP8 video decoder is implemented by partitioning the required functions across multiple sub systems, with an optimal mapping to existing functional blocks. Key optimizations include the reuse of hardware designed for prior generation VP6 and VP7 decoders. In order to reduce implementation complexity, cost and power consumption, a non-exact, approximate deblocking loop filter is implemented.
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