公开(公告)号：US10423414B2

公开(公告)日：2019-09-24

申请号：US14539674

申请日：2014-11-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ajit Deepak Gupte ,  Mahesh Mehendale ,  Navin Acharya ,  Mel Alan Phipps

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/38 ,  G06T1/20

Abstract: In an embodiment, a device including a processor, a plurality of hardware accelerator engines and a hardware scheduler is disclosed. The processor is configured to schedule an execution of a plurality of instruction threads, where each instruction thread includes a plurality of instructions associated with an execution sequence. The plurality of hardware accelerator engines performs the scheduled execution of the plurality of instruction threads. The hardware scheduler is configured to control the scheduled execution such that each hardware accelerator engine is configured to execute a corresponding instruction and the plurality of instructions are executed by the plurality of hardware accelerator engines in a sequential manner. The plurality of instruction threads are executed by plurality of hardware accelerator engines in a parallel manner based on the execution sequence and an availability status of each of the plurality of hardware accelerator engines.

公开(公告)号：US20160132329A1

公开(公告)日：2016-05-12

申请号：US14539674

申请日：2014-11-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ajit Deepak Gupte ,  Mahesh Mehendale ,  Navin Acharya ,  Mel Alan Phipps

IPC: G06F9/30 ,  G06F9/48

Abstract: In an embodiment, a device including a processor, a plurality of hardware accelerator engines and a hardware scheduler is disclosed. The processor is configured to schedule an execution of a plurality of instruction threads, where each instruction thread includes a plurality of instructions associated with an execution sequence. The plurality of hardware accelerator engines performs the scheduled execution of the plurality of instruction threads. The hardware scheduler is configured to control the scheduled execution such that each hardware accelerator engine is configured to execute a corresponding instruction and the plurality of instructions are executed by the plurality of hardware accelerator engines in a sequential manner. The plurality of instruction threads are executed by plurality of hardware accelerator engines in a parallel manner based on the execution sequence and an availability status of each of the plurality of hardware accelerator engines.

Abstract translation: 在一个实施例中，公开了一种包括处理器，多个硬件加速器引擎和硬件调度器的设备。 处理器被配置为调度多个指令线程的执行，其中每个指令线程包括与执行序列相关联的多个指令。 多个硬件加速器引擎执行多个指令线程的调度执行。 硬件调度器被配置为控制调度的执行，使得每个硬件加速器引擎被配置为执行相应的指令，并且多个指令由多个硬件加速器引擎以顺序的方式执行。 基于执行顺序和多个硬件加速器引擎中的每一个的可用性状态，多个指令线程以并行方式由多个硬件加速器引擎执行。