公开(公告)号：US20240036866A1

公开(公告)日：2024-02-01

申请号：US18355939

申请日：2023-07-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Bui ,  Timothy D. Anderson ,  Paul Gauvreau

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3802 ,  G06F9/3836

Abstract: Disclosed herein are systems and methods for executing multiple instruction set architectures (ISAs) on a singular processing unit. In an implementation, a processor that includes a first decoder, a second decoder, instruction fetch circuitry, and instruction dispatch circuitry is configured to execute two separate instruction set architectures. In an implementation, the instruction fetch circuitry is configured to fetch instructions from an associated memory. In an implementation the instruction dispatch circuitry is coupled to the instruction fetch circuitry, the first decoder, and the second decoder and is configured to route instructions associated with a first ISA to the first decoder, and route instructions associated with a second ISA to the second decoder.

公开(公告)号：US12260219B2

公开(公告)日：2025-03-25

申请号：US18355939

申请日：2023-07-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Bui ,  Timothy D. Anderson ,  Paul Gauvreau

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed herein are systems and methods for executing multiple instruction set architectures (ISAs) on a singular processing unit. In an implementation, a processor that includes a first decoder, a second decoder, instruction fetch circuitry, and instruction dispatch circuitry is configured to execute two separate instruction set architectures. In an implementation, the instruction fetch circuitry is configured to fetch instructions from an associated memory. In an implementation the instruction dispatch circuitry is coupled to the instruction fetch circuitry, the first decoder, and the second decoder and is configured to route instructions associated with a first ISA to the first decoder, and route instructions associated with a second ISA to the second decoder.