公开(公告)号：US20180253122A1

公开(公告)日：2018-09-06

申请号：US15911138

申请日：2018-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Paul Joseph Kramer ,  Matthew Hansen Childs ,  Robert Callaghan Taft

IPC: G06F1/08 ,  H03K5/01

Abstract: Clock generation for capturing a repetitive signal relative to a clock includes clock circuitry to provide a clock with active and inactive clock edges within a clock period, and signal capture circuitry to capture repetitive signal transitions at an active clock edge, based on pre-defined setup and hold times which determine a setup/hold window. Clock phase adjustment circuitry is configured to adjust clock phase so that the repetitive signal transitions occur within a signal capture window between setup/hold windows. Clock phase adjustment can be based on: aligning the clock inactive edges to the repetitive signal transitions; and/or averaging successive phase comparisons of the clock and the repetitive signal transitions; and/or selectively performing an initial polarity inversion to generate a polarity inverted clock, and then adjusting clock phase of the polarity inverted clock. An example implementation is JESD204B (subclass1) to adjust DEVCLK phase relative to a SYSREF timing reference control signal.

公开(公告)号：US10775833B2

公开(公告)日：2020-09-15

申请号：US15911138

申请日：2018-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Paul Joseph Kramer ,  Matthew Hansen Childs ,  Robert Callaghan Taft

IPC: G06F1/10 ,  H03K5/01 ,  G06F1/08 ,  H03K5/00

Abstract: Clock generation for capturing a repetitive signal relative to a clock includes clock circuitry to provide a clock with active and inactive clock edges within a clock period, and signal capture circuitry to capture repetitive signal transitions at an active clock edge, based on pre-defined setup and hold times which determine a setup/hold window. Clock phase adjustment circuitry is configured to adjust clock phase so that the repetitive signal transitions occur within a signal capture window between setup/hold windows. Clock phase adjustment can be based on: aligning the clock inactive edges to the repetitive signal transitions; and/or averaging successive phase comparisons of the clock and the repetitive signal transitions; and/or selectively performing an initial polarity inversion to generate a polarity inverted clock, and then adjusting clock phase of the polarity inverted clock. An example implementation is JESD204B (subclass1) to adjust DEVCLK phase relative to a SYSREF timing reference control signal.