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公开(公告)号：US20210356984A1
公开(公告)日：2021-11-18
申请号：US17386591
申请日：2021-07-28
Applicant: Texas Instruments Incorporated
Inventor： Robert Callaghan Taft , Vineethraj Rajappan Nair
Abstract: An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.
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公开(公告)号：US11177251B2
公开(公告)日：2021-11-16
申请号：US16780933
申请日：2020-02-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: An electronic circuit includes an electronic device, an input/output terminal, and a protection device. The electronic device includes a signal terminal to receive an input signal. The input/output terminal is configured to receive the input signal from a source external to the electronic circuit. The protection device is coupled to the electronic device and to the input/output terminal. The protection device is configured to protect the electronic device from voltage of the input signal exceeding a threshold. The protection device includes a first semiconductor region, a first contact, and a second contact. The first contact connects the first semiconductor region to the input/output terminal. The second contact connects the first semiconductor region to the signal terminal of the electronic device.
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公开(公告)号：US11429136B2
公开(公告)日：2022-08-30
申请号：US17386591
申请日：2021-07-28
Applicant: Texas Instruments Incorporated
Inventor： Robert Callaghan Taft , Vineethraj Rajappan Nair
Abstract: An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.
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公开(公告)号：US11106236B2
公开(公告)日：2021-08-31
申请号：US16935240
申请日：2020-07-22
Applicant: Texas Instruments Incorporated
Inventor： Robert Callaghan Taft , Vineethraj Rajappan Nair
Abstract: An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.
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公开(公告)号：US10547295B2
公开(公告)日：2020-01-28
申请号：US15974956
申请日：2018-05-09
Applicant: Texas Instruments Incorporated
Inventor： Robert Callaghan Taft , Vineethraj Rajappan Nair
Abstract: In described examples, an electronic circuit for delaying a signal (received at an input node) includes a delay line with multiple tap locations, a tap line proximate to the delay line and coupled to an output node, and multiple groups of switches. Switches in the groups of switches are severally coupled between tap locations corresponding to the respective group of switches, and the tap line. When the signal is propagated through the delay line, a first number of the switches corresponding to a selected tap location are closed, a second number of the switches corresponding to an adjacent tap location are closed, and the signal is transmitted with a delay through the closed switches, to the tap line, to the output node. The delay includes an average, weighted using the first and second numbers, of delays corresponding to the selected and adjacent tap locations.
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Patent Agency Ranking
公开(公告)号：US10382025B2
公开(公告)日：2019-08-13
申请号：US15933021
申请日：2018-03-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robert Callaghan Taft
Abstract: A circuit includes a plurality of series-coupled delay buffers and a plurality of logic gates. Each logic gate includes first and second inputs. The first input of each logic gate is coupled to a corresponding one of the delay buffers. The circuit also includes a plurality of flip-flops. Each flip-flop includes a data input and a data output. The data input is coupled to an output of a corresponding one of the logic gates and the data output is coupled to the second input of one of the corresponding logic gates.
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公开(公告)号：US11011508B2
公开(公告)日：2021-05-18
申请号：US16220881
申请日：2018-12-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: An electronic device, e.g. an integrated circuit, is formed on a P-type lightly-doped semiconductor substrate having an N-type buried layer. First and second N-wells extend from a surface of the substrate to the buried layer. A first NSD region is located within the first N-well, and a second NSD region is located within the second N-well. A PSD region extends from the substrate surface into the substrate and is located between the first and second NSD regions. A P-type lightly-doped portion of the substrate is located between the N-well and the substrate surface and between the PSD region and the first and second NSD regions.
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公开(公告)号：US10593661B2
公开(公告)日：2020-03-17
申请号：US15825813
申请日：2017-11-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: An electronic circuit includes an electronic device, an input/output terminal, and a protection device. The electronic device includes a signal terminal to receive an input signal. The input/output terminal is configured to receive the input signal from a source external to the electronic circuit. The protection device is coupled to the electronic device and to the input/output terminal. The protection device is configured to protect the electronic device from voltage of the input signal exceeding a threshold. The protection device includes a first semiconductor region, a first contact, and a second contact. The first contact connects the first semiconductor region to the input/output terminal. The second contact connects the first semiconductor region to the signal terminal of the electronic device.
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公开(公告)号：US20180337665A1
公开(公告)日：2018-11-22
申请号：US15974956
申请日：2018-05-09
Applicant: Texas Instruments Incorporated
Inventor： Robert Callaghan Taft , Vineethraj Rajappan Nair
IPC: H03K5/14
CPC classification number: H03K5/14 , H03K2005/00019
Abstract: In described examples, an electronic circuit for delaying a signal (received at an input node) includes a delay line with multiple tap locations, a tap line proximate to the delay line and coupled to an output node, and multiple groups of switches. Switches in the groups of switches are severally coupled between tap locations corresponding to the respective group of switches, and the tap line. When the signal is propagated through the delay line, a first number of the switches corresponding to a selected tap location are closed, a second number of the switches corresponding to an adjacent tap location are closed, and the signal is transmitted with a delay through the closed switches, to the tap line, to the output node. The delay includes an average, weighted using the first and second numbers, of delays corresponding to the selected and adjacent tap locations.
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公开(公告)号：US10116319B2
公开(公告)日：2018-10-30
申请号：US15911141
申请日：2018-03-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Robert Callaghan Taft , Alexander Bodem
Abstract: A circuit including an amplifier array including an amplifier stage with M amplifiers (M≥2), connected to a resistor interpolator (interpolation order N≥2) including an input row and at least a second row, each row comprising interpolation resistors connected in series at nodes. The input row including M driven nodes connected to a respective amplifier, and connected in parallel to the second row, with at least some first-row interpolation nodes connected to corresponding second-row interpolation nodes. The resistor interpolator comprising at least one multi-row interpolation cell, with: in the input row, a driven node coupled through first and second interpolation resistors to respective adjacent first and second interpolation nodes; and in the second row, third and fourth interpolation nodes coupled through third and fourth interpolation resistors to an intermediate fifth interpolation node; and with the first and second interpolation nodes connected respectively to the third and fourth interpolation nodes.
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