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公开(公告)号:US11125820B2
公开(公告)日:2021-09-21
申请号:US16189431
申请日:2018-11-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Robert Mason Hanrahan
IPC: G01R31/327 , H02H3/16 , H02H3/33 , G01R19/165
Abstract: An apparatus includes a safety fault interrupter circuit. The safety fault interrupter circuit includes a safety fault monitor coupled to a first bias node and configured to selectively assert a fault interrupter signal based at least in part on a first bias voltage and a first power consumption. The safety fault interrupter circuit also includes a power fault monitor for the safety fault monitor, wherein the power fault monitor is coupled to a second bias node and is configured to selectively assert the fault interrupter signal based at least in part on a second bias voltage and a second power consumption that is less than the first power consumption.
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公开(公告)号:US10789399B2
公开(公告)日:2020-09-29
申请号:US16540121
申请日:2019-08-14
Applicant: Texas Instruments Incorporated
Inventor: Srikanth Pam , Yudhister Satija , Pradeep Kumar Chawda , Makram Mounzer Mansour , Robert Mason Hanrahan , Jeffrey Robert Perry
IPC: G06F30/30 , G06F30/373 , G06F119/06 , G06F119/10 , G06F30/36
Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.
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公开(公告)号:US11853664B2
公开(公告)日:2023-12-26
申请号:US17486986
申请日:2021-09-28
Applicant: Texas Instruments Incorporated
Inventor: Srikanth Pam , Yudhister Satija , Pradeep Kumar Chawda , Makram Mounzer Mansour , Robert Mason Hanrahan , Jeffrey Robert Perry
IPC: G06F30/30 , G06F30/373 , G06F119/06 , G06F119/10 , G06F30/36
CPC classification number: G06F30/30 , G06F30/373 , G06F30/36 , G06F2119/06 , G06F2119/10
Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.
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公开(公告)号:US11163926B2
公开(公告)日:2021-11-02
申请号:US16995868
申请日:2020-08-18
Applicant: Texas Instruments Incorporated
Inventor: Srikanth Pam , Yudhister Satija , Pradeep Kumar Chawda , Makram Mounzer Mansour , Robert Mason Hanrahan , Jeffrey Robert Perry
IPC: G06F30/30 , G06F30/373 , G06F119/06 , G06F119/10 , G06F30/36
Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.
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公开(公告)号:US20200380187A1
公开(公告)日:2020-12-03
申请号:US16995868
申请日:2020-08-18
Applicant: Texas Instruments Incorporated
Inventor: Srikanth Pam , Yudhister Satija , Pradeep Kumar Chawda , Makram Mounzer Mansour , Robert Mason Hanrahan , Jeffrey Robert Perry
IPC: G06F30/30 , G06F30/373
Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.
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公开(公告)号:US20200067346A1
公开(公告)日:2020-02-27
申请号:US16669114
申请日:2019-10-30
Applicant: Texas Instruments Incorporated
Inventor: Deric Wayne Waters , Robert Mason Hanrahan
Abstract: A power provider circuit includes a plurality of power delivery controllers, a single stage power supply, and control circuitry. Each of the plurality of power delivery controllers is configured to provide power to a detachable device. The single stage power supply is configured to generate the power for provision to the detachable devices, and to provide the power at a plurality of selectable voltages. The control circuitry configured to select a given voltage of the plurality of selectable voltages to be made available via all of the power delivery controllers based on power utilization capabilities and other optional status indications reported by the detachable devices.
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公开(公告)号:US20190370428A1
公开(公告)日:2019-12-05
申请号:US16540121
申请日:2019-08-14
Applicant: Texas Instruments Incorporated
Inventor: Srikanth Pam , Yudhister Satija , Pradeep Kumar Chawda , Makram Mounzer Mansour , Robert Mason Hanrahan , Jeffrey Robert Perry
IPC: G06F17/50
Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.
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公开(公告)号:US11867761B2
公开(公告)日:2024-01-09
申请号:US17407253
申请日:2021-08-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Robert Mason Hanrahan
IPC: H02H3/16 , G01R31/327 , H02H3/33 , G01R19/165
CPC classification number: G01R31/3274 , G01R31/3275 , H02H3/162 , H02H3/335 , G01R19/16547
Abstract: An apparatus includes a safety fault interrupter circuit. The safety fault interrupter circuit includes a safety fault monitor coupled to a first bias node and configured to selectively assert a fault interrupter signal based at least in part on a first bias voltage and a first power consumption. The safety fault interrupter circuit also includes a power fault monitor for the safety fault monitor, wherein the power fault monitor is coupled to a second bias node and is configured to selectively assert the fault interrupter signal based at least in part on a second bias voltage and a second power consumption that is less than the first power consumption.
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公开(公告)号:US11239694B2
公开(公告)日:2022-02-01
申请号:US16669114
申请日:2019-10-30
Applicant: Texas Instruments Incorporated
Inventor: Deric Wayne Waters , Robert Mason Hanrahan
Abstract: A power provider circuit includes a plurality of power delivery controllers, a single stage power supply, and control circuitry. Each of the plurality of power delivery controllers is configured to provide power to a detachable device. The single stage power supply is configured to generate the power for provision to the detachable devices, and to provide the power at a plurality of selectable voltages. The control circuitry configured to select a given voltage of the plurality of selectable voltages to be made available via all of the power delivery controllers based on power utilization capabilities and other optional status indications reported by the detachable devices.
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公开(公告)号:US20220012391A1
公开(公告)日:2022-01-13
申请号:US17486986
申请日:2021-09-28
Applicant: Texas Instruments Incorporated
Inventor: Srikanth Pam , Yudhister Satija , Pradeep Kumar Chawda , Makram Mounzer Mansour , Robert Mason Hanrahan , Jeffrey Robert Perry
IPC: G06F30/30 , G06F30/373
Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.
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