公开(公告)号：US20240346224A1

公开(公告)日：2024-10-17

申请号：US18757046

申请日：2024-06-27

申请人： Mahesh K. Kumashikar ,  Atul Maheshwari ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Krishna Bharath Kolluru

发明人： Mahesh K. Kumashikar ,  Atul Maheshwari ,  MD Altaf Hossain ,  Ankireddy Nalamalpu ,  Krishna Bharath Kolluru

IPC分类号： G06F30/392 ,  G06F30/33 ,  G06F119/10

CPC分类号： G06F30/392 ,  G06F30/33 ,  G06F2119/10

摘要： Systems or methods of the present disclosure may provide a multi-chip package with two or more integrated circuit devices that each include hybrid bumps. The hybrid bumps may include bumps of different sizes to facilitate different types of communication. For example, the hybrid bumps may include a first bump with fine pitch for die-to-die communication and/or a second bump with a large pitch for off-package communication. The multi-chip package may include a bridge to facilitate signal transfer between the integrated circuit device with the hybrid bumps and other components within the multi-chip package. Additionally or alternatively, the multi-chip package may include an interconnect to facilitate signal transfer between two integrated circuit devices. The interconnect may include fine pitch bumps, which may be translated by an interposer to a pitch size of the bridge. As such, the interconnect may facilitate die-to-die communication and/or off-package communication.

公开(公告)号：US12099792B2

公开(公告)日：2024-09-24

申请号：US18341400

申请日：2023-06-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hsien Yu Tseng ,  Amit Kundu ,  Chun-Wei Chang ,  Szu-Lin Liu ,  Sheng-Feng Liu

IPC分类号： G06F30/398 ,  G06F111/20 ,  G06F119/08 ,  G06F119/10 ,  H01L29/78

CPC分类号： G06F30/398 ,  G06F2111/20 ,  G06F2119/08 ,  G06F2119/10 ,  H01L29/785

摘要： An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.

公开(公告)号：US11928396B2

公开(公告)日：2024-03-12

申请号：US16556956

申请日：2019-08-30

申请人： TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.

发明人： Brian T. Thurgate ,  Daniel B. Gidcumb

IPC分类号： G06F30/15 ,  G06F30/20 ,  G06F111/10 ,  G06F119/10

CPC分类号： G06F30/15 ,  G06F30/20 ,  G06F2111/10 ,  G06F2119/10

摘要： Disclosed is a method for evaluating computational fluid dynamic simulation results. The method includes: performing at least two baseline runs of a simulated area or volume containing a first vehicle body shape using a set of initial conditions, performing a change run using a second vehicle body using the set of initial conditions, creating a noise map based on differences between the second baseline run and the first baseline run, creating a change map based on differences between the change run and a selected baseline run, and comparing the change map to the noise map.

公开(公告)号：US11875099B2

公开(公告)日：2024-01-16

申请号：US17397197

申请日：2021-08-09

申请人： International Business Machines Corporation

发明人： Gerald L Strevig, III ,  Adam P. Matheny ,  Alice Hwajin Lee ,  Jose Luis Pontes Correia Neves

IPC分类号： G06F30/327 ,  G06F30/394 ,  G06F119/10

CPC分类号： G06F30/327 ,  G06F30/394 ,  G06F2119/10

摘要： Examples described herein provide a computer-implemented method that includes identifying, by a processing device, a victim/aggressor pair of nets for an integrated circuit. The method further includes severing nets of the victim/aggressor pair of nets. The method further includes swapping severed segments of the nets. The method further includes rerouting the nets subsequent to swapping the severed segments of the nets.

公开(公告)号：US11847397B1

公开(公告)日：2023-12-19

申请号：US18165886

申请日：2023-02-07

申请人： Worldwide Pro Ltd.

发明人： William Wai Yan Ho

IPC分类号： G06F30/20 ,  G06F30/392 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398 ,  G06F119/10

CPC分类号： G06F30/392 ,  G06F30/20 ,  G06F30/327 ,  G06F30/367 ,  G06F30/398 ,  G06F2119/10

摘要： Any primitive cells or blocks can be represented physically by a Barycenter compact model (or Barycenter model), and any black box model can also be physically represented by a Barycenter compact model physically. A boundary condition between blocks is formulated by the Barycenter compact model. Boundary condition problems between blocks can be limited within two levels only if using the Barycenter compact model.

公开(公告)号：US11714949B2

公开(公告)日：2023-08-01

申请号：US17314988

申请日：2021-05-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Hua Liu ,  Yun-Xiang Lin ,  Yuan-Te Hou ,  Chung-Hsing Wang

IPC分类号： G06F30/00 ,  G06F30/398 ,  G06F30/367 ,  G06F30/20 ,  G06F30/39 ,  G06F119/10 ,  G06F30/392 ,  G06F119/18 ,  G06F111/20

CPC分类号： G06F30/398 ,  G06F30/20 ,  G06F30/367 ,  G06F30/39 ,  G06F30/392 ,  G06F2111/20 ,  G06F2119/10 ,  G06F2119/18

摘要： A method includes: identifying attributes that are associated with cell edges of abutted cells in a layout of a semiconductor device, wherein the attributes include at least one of terminal types of the cell edges; determining at least one minimal boundary leakage of the abutted cells based on the attributes, for adjustment of the layout of the semiconductor device. A system is also disclosed herein.

公开(公告)号：US11182531B2

公开(公告)日：2021-11-23

申请号：US16512566

申请日：2019-07-16

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Shayak Banerjee ,  William Brearley

IPC分类号： G06F30/398 ,  G06F30/33 ,  G06F30/3323 ,  G06N7/00 ,  G06F17/18 ,  G06F111/08 ,  G06F119/10

摘要： A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.

公开(公告)号：US11163934B2

公开(公告)日：2021-11-02

申请号：US16404816

申请日：2019-05-07

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Shayak Banerjee ,  William Brearley

IPC分类号： G06F30/398 ,  G06F30/33 ,  G06F30/3323 ,  G06N7/00 ,  G06F17/18 ,  G06F111/08 ,  G06F119/10

摘要： A method and system is provided for detecting at risk structures due to mask overlay that occur during lithography processes. The method can be implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to obtain a simulation of a metal layer and a via, and determine a probability that an arbitrary point (x, y) on the metal layer is covered by the via by calculating a statistical coverage area metric followed by mathematical approximations of a summing function.

公开(公告)号：US11042674B2

公开(公告)日：2021-06-22

申请号：US15729216

申请日：2017-10-10

申请人： Dassault Systemes Simulia Corp.

发明人： Adrien Mann ,  Chenghai Sun ,  Hudong Chen ,  Raoyang Zhang ,  Franck Léon Pérot

IPC分类号： G06F30/20 ,  G06F30/15 ,  G06F30/23 ,  G06F119/10

摘要： The description describes one or more processing devices and one or more hardware storage devices storing instructions that are operable, when executed by the one or more processing devices, to cause the one or more processing devices to perform operations including modeling the porous material as a two-dimensional interface, in a simulation space, in which fluid flows and sound waves travel through the porous material and experience pressure and acoustic losses. The operations also include simulating, in the simulation space, fluid flow and propagation of sound waves, the activity of the fluid being simulated so as to simulate movement of elements within the simulation space and across the interface, where the simulation of the movement of the elements across the interface is governed by the model.

公开(公告)号：US11038471B2

公开(公告)日：2021-06-15

申请号：US16678696

申请日：2019-11-08

申请人： Skyworks Solutions, Inc.

发明人： Serge Francois Drogi ,  Florinel G. Balteanu ,  Shayan Farahvash

IPC分类号： H03F1/30 ,  H03F1/02 ,  H03F3/195 ,  H03F3/24 ,  G06F30/367 ,  G06F119/06 ,  G06F119/10

摘要： Envelope tracking systems with modeling for power amplifier supply voltage filtering are provided herein. In certain embodiments, an envelope tracking system includes a supply voltage filter, a power amplifier that receives a power amplifier supply voltage through the supply voltage filter, and an envelope tracker that generates the power amplifier supply voltage. The power amplifier provides amplification to a radio frequency (RF) signal that is generated based on digital signal data, and the envelope tracker generates the power amplifier supply voltage based on an envelope signal corresponding to an envelope of the RF signal. The envelope tracking system further includes digital modeling circuitry that models the supply voltage filter and operates to digitally compensate the digital signal data for effects of the supply voltage filter, such as distortion.