公开(公告)号：US09811112B2

公开(公告)日：2017-11-07

申请号：US14997862

申请日：2016-01-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subrahmanya Bharathi Akondy ,  Steven Brett Larimore

IPC: G06F1/12

CPC classification number: G06F1/12

Abstract: A system includes a CPU, a serial interface, and an adaptive clock delay compensator. The adaptive clock delay compensator is configured to generate a clock signal at a first frequency, detect an edge on a data signal, and count the number of clock cycles of a counter clock to measure the delay between an edge of the clock signal and the detected edge on the data signal to produce a first delay value. The CPU is configured to convert the first delay value to a different clock domain at a second frequency to produce a converted delay value, and initiate a data transfer operation using the second frequency as a clock signal. The adaptive clock delay compensator is configured to generate a delayed clock signal at the second frequency to the serial interface that is delayed from the clock signal at the second frequency by the converted delay value.