公开(公告)号：US20200186394A1

公开(公告)日：2020-06-11

申请号：US16790475

申请日：2020-02-13

Applicant: Texas Instruments Incorporated

Inventor： Zhidong Liu ,  James Michael Walden ,  Satish Kumar Vemuri

IPC: H04L25/02 ,  H03K7/06 ,  H01L29/78 ,  G05F3/26 ,  H04L27/227 ,  H04L25/06 ,  H04B1/04

Abstract: Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.

公开(公告)号：US20200099551A1

公开(公告)日：2020-03-26

申请号：US16425536

申请日：2019-05-29

Applicant: Texas Instruments Incorporated

Inventor： Zhidong Liu ,  James Michael Walden ,  Satish Kumar Vemuri

IPC: H04L25/02 ,  G05F3/26 ,  H04L27/227 ,  H01L29/78

Abstract: Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.

公开(公告)号：US10784776B2

公开(公告)日：2020-09-22

申请号：US16126666

申请日：2018-09-10

Applicant: Texas Instruments Incorporated

Inventor： Danyang Zhu ,  Zhidong Liu

IPC: H04B1/18 ,  H04B1/38 ,  H04B3/28 ,  H02M3/07

Abstract: An isolation device provides high common mode transient immunity without increasing the supply voltage rails in the transmitter side. In one aspect, the disclosed isolation device implements a self-boosting scheme to increase a voltage swing of a transmission signal under a lesser supply voltage rail. The disclosed isolation device includes a first stage circuit, a boost circuit, and a second stage circuit. The first stage circuit is configured to generate first and second signals each having a first voltage within a supply voltage range. The boost circuit is configured to provide a boosted voltage range greater than the supply voltage range responsive to at least one of the first or second signal. The second stage circuit is configured to generate an output signal based on either one of the first or second signal, such that the output signal has a second voltage within the boosted voltage range.

公开(公告)号：US20200083804A1

公开(公告)日：2020-03-12

申请号：US16126666

申请日：2018-09-10

Applicant: Texas Instruments Incorporated

Inventor： Danyang Zhu ,  Zhidong Liu

IPC: H02M3/07

Abstract: An isolation device provides high common mode transient immunity without increasing the supply voltage rails in the transmitter side. In one aspect, the disclosed isolation device implements a self-boosting scheme to increase a voltage swing of a transmission signal under a lesser supply voltage rail. The disclosed isolation device includes a first stage circuit, a boost circuit, and a second stage circuit. The first stage circuit is configured to generate first and second signals each having a first voltage within a supply voltage range. The boost circuit is configured to provide a boosted voltage range greater than the supply voltage range responsive to at least one of the first or second signal. The second stage circuit is configured to generate an output signal based on either one of the first or second signal, such that the output signal have a second voltage within the boosted voltage range.

公开(公告)号：US12237836B2

公开(公告)日：2025-02-25

申请号：US17710533

申请日：2022-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kyoung Min Lee ,  Satish Kumar Vemuri ,  Zhidong Liu ,  Maxim James Franke ,  Kory Andrew McCarthy

IPC: H03K5/00 ,  H03K3/012 ,  H03K5/1252

Abstract: In some examples, a circuit includes a capacitor having a first terminal and a second terminal, the first terminal coupled to a voltage supply terminal of the circuit. The circuit also includes a transistor having a transistor gate, a transistor drain, and a transistor source, the transistor source coupled to ground and the transistor drain coupled to an input terminal of the circuit. The transistor is configured to conduct responsive to a gate signal received at the transistor gate, the gate signal based on a signal provided at the second terminal of the capacitor. The circuit also includes a Schmitt trigger having a Schmitt trigger input coupled to the transistor drain.

公开(公告)号：US10601614B1

公开(公告)日：2020-03-24

申请号：US16425536

申请日：2019-05-29

Applicant: Texas Instruments Incorporated

Inventor： Zhidong Liu ,  James Michael Walden ,  Satish Kumar Vemuri

IPC: H04L25/02 ,  H01L29/78 ,  H04L27/227 ,  G05F3/26 ,  H04B1/04 ,  H04L25/06 ,  H03K7/06

Abstract: Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.