Device with isolation barrier and fault detection

    公开(公告)号:US10992293B2

    公开(公告)日:2021-04-27

    申请号:US16137146

    申请日:2018-09-20

    IPC分类号: H03K17/08 H03K17/081

    摘要: A device that comprises a first semiconductor die and a second semiconductor die. The first semiconductor die comprises a first clock signal generator. The second semiconductor die comprises a fault detection circuit, the fault detection circuit comprising a second clock signal generator, a first counter coupled to the second clock signal generator, multiple storage devices coupled to the second clock signal generator and to the first counter, a logic gate coupled to the multiple storage devices, a second counter coupled to the logic gate and to the first clock signal generator, and a comparator coupled to the logic gate and the second counter.

    High voltage level shifter with short propagation delay

    公开(公告)号:US10230372B2

    公开(公告)日:2019-03-12

    申请号:US15959176

    申请日:2018-04-21

    摘要: A lever shifter includes an output driver and a high-side gate driver. The high-side gate driver is configured to drive the high-side output transistor, and is coupled to an on pulse signal line that conducts an on pulse, and is coupled to an off pulse signal line that conducts an off pulse. The high-side gate driver includes a blocking circuit configured to enable generation of a drive signal to the high-side output transistor based on a voltage of a first of the on or off pulse signal line being greater than a first predetermined amount and a voltage of a second of the on or off signal line being less than a second predetermined amount.

    High voltage level shifter with short propagation delay

    公开(公告)号:US10374606B2

    公开(公告)日:2019-08-06

    申请号:US16260428

    申请日:2019-01-29

    摘要: A lever shifter includes an output driver and a high-side gate driver. The high-side gate driver is configured to drive the high-side output transistor, and is coupled to an on pulse signal line that conducts an on pulse, and is coupled to an off pulse signal line that conducts an off pulse. The high-side gate driver includes a blocking circuit configured to enable generation of a drive signal to the high-side output transistor based on a voltage of a first of the on or off pulse signal line being greater than a first predetermined amount and a voltage of a second of the on or off signal line being less than a second predetermined amount.

    Pre-Bias Startup of a Converter
    8.
    发明申请

    公开(公告)号:US20170201171A1

    公开(公告)日:2017-07-13

    申请号:US15408101

    申请日:2017-01-17

    IPC分类号: H02M1/36 H02M3/335

    摘要: A method includes comparing, by a voltage-second (VS) controller, a first duty cycle used to control a first switch at a primary side of a power transformer of a DC-to-DC converter with a threshold. The method further includes if a value of the first duty cycle is less than the threshold, controlling, by the VS controller, a second duty cycle used to control a second switch at a secondary side of the power transformer, and maintaining a voltage level at an output voltage node at a non-zero value, and if the value of the first duty cycle is greater than the threshold, controlling, by an output voltage loop, the second duty cycle based on the first duty cycle, and monotonically increasing the voltage level the at the output voltage node from the non-zero value to a predetermined value.

    Pre-bias startup of a converter
    9.
    发明授权
    Pre-bias startup of a converter 有权
    转换器的预偏置启动

    公开(公告)号:US09548653B2

    公开(公告)日:2017-01-17

    申请号:US14626650

    申请日:2015-02-19

    IPC分类号: H02M3/335 H02M1/36

    摘要: A method includes comparing, by a voltage-second (VS) controller, a first duty cycle used to control a first switch at a primary side of a power transformer of a DC-to-DC converter with a threshold. The method further includes if a value of the first duty cycle is less than the threshold, controlling, by the VS controller, a second duty cycle used to control a second switch at a secondary side of the power transformer, and maintaining a voltage level at an output voltage node at a non-zero value, and if the value of the first duty cycle is greater than the threshold, controlling, by an output voltage loop, the second duty cycle based on the first duty cycle, and monotonically increasing the voltage level the at the output voltage node from the non-zero value to a predetermined value.

    摘要翻译: 一种方法包括通过电压 - 秒(VS)控制器比较用于控制具有阈值的DC-DC转换器的电力变压器的初级侧的第一开关的第一占空比。 该方法还包括如果第一占空比的值小于阈值,则由VS控制器控制用于控制电力变压器次级侧的第二开关的第二占空比,并且将电压电平保持在 输出电压节点处于非零值,并且如果第一占空比的值大于阈值,则通过输出电压环路基于第一占空比控制第二占空比,并且单调地增加电压 将输出电压节点处的非零值电平为预定值。

    METHOD AND CIRCUITRY FOR ON-CHIP ELECTRO-STATIC DISCHARGE PROTECTION SCHEME FOR LOW COST GATE DRIVER INTEGRATED CIRCUIT
    10.
    发明申请
    METHOD AND CIRCUITRY FOR ON-CHIP ELECTRO-STATIC DISCHARGE PROTECTION SCHEME FOR LOW COST GATE DRIVER INTEGRATED CIRCUIT 审中-公开
    用于低成本门驱动器集成电路的片上电静电放电保护方案的方法和电路

    公开(公告)号:US20160126233A1

    公开(公告)日:2016-05-05

    申请号:US14533432

    申请日:2014-11-05

    IPC分类号: H01L27/02

    摘要: An apparatus includes an integrated circuit, a plurality of bi-directional pins, and an electro-static discharge (ESD) clamp. The integrated circuit is configured to provide a ground potential. The plurality of bi-directional pins are configured to provide a differential input signal for the integrated circuit. The electro-static discharge (ESD) clamp is coupled between the ground potential and the plurality of bi-directional pins.

    摘要翻译: 一种装置包括集成电路,多个双向引脚和静电放电(ESD)钳位。 集成电路被配置为提供接地电位。 多个双向引脚被配置为提供用于集成电路的差分输入信号。 静电放电(ESD)钳位电极耦合在地电位和多个双向引脚之间。